Cypress CY7C1146V18 User Manual

CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

18-Mbit DDR-II+ SRAM 2-Word Burst

Architecture (2.0 Cycle Read Latency)

Features

Functional Description

■ 18 Mbit density (2M x 8, 2M x 9, 1M x 18, 512K x 36)

■ 300 MHz to 375 MHz clock for high bandwidth

■ 2-Word burst for reducing address bus frequency

The CY7C1146V18, CY7C1157V18, CY7C1148V18, and

CY7C1150V18 are 1.8V Synchronous Pipelined SRAMs

equipped with DDR-II+ architecture. The DDR-II+ consists of an

SRAM core with advanced synchronous peripheral circuitry.

Addresses for read and write are latched on alternate rising

edges of the input (K) clock. Write data is registered on the rising

edges of both K and K. Read data is driven on the rising edges

of K and K. Each address location is associated with two 8-bit

words (CY7C1146V18) or 9-bit words (CY7C1157V18) or 18-bit

words (CY7C1148V18) or 36-bit words (CY7C1150V18) that

burst sequentially into or out of the device.

■ Double Data Rate (DDR) interfaces

(data transferred at 750 MHz) at 375 MHz

■ Read latency of 2.0 clock cycles

■ Two input clocks (K and K) for precise DDR timing

❐ SRAM uses rising edges only

Asynchronous inputs include output impedance matching input

■ Echo clocks (CQ and CQ) simplify data capture in high-speed

systems

(ZQ). Synchronous data outputs (Q, sharing the same physical

pins as the data inputs D) are tightly matched to the two output

echo clocks CQ/CQ, eliminating the need for separately

capturing data from each individual DDR SRAM in the system

design.

■ Data valid pin (QVLD) to indicate valid data on the output

■ Synchronous internally self-timed writes

[1]

■ Core V = 1.8V ± 0.1V; IO V

= 1.4V to V

DDQ

All synchronous inputs pass through input registers controlled by

the K or K input clocks. All data outputs pass through output

registers controlled by the K or K input clocks. Writes are

conducted with on-chip synchronous self-timed write circuitry.

■ HSTL inputs and Variable drive HSTL output buffers

■ Available in 165-Ball FBGA package (13 x 15 x 1.4 mm)

■ Offered in both Pb-free and non Pb-free packages

■ JTAG 1149.1-compatible test access port

■ Delay Lock Loop (DLL) for accurate data placement

Configurations

With Read Cycle Latency of 2.0 cycles:

CY7C1146V18 – 2M x 8

CY7C1157V18 – 2M x 9

CY7C1148V18 – 1M x 18

CY7C1150V18 – 512K x 36

Selection Guide

Description

Maximum Operating Frequency

Maximum Operating Current

375 MHz

375

333 MHz

333

300 MHz

300

Unit

MHz

1020

920

850

Note

1. The QDR consortium specification for V

is 1.5V + 0.1V. The Cypress QDR devices exceed the QDR consortium specification and are capable of supporting V

DDQ

= 1.4V to V

Cypress Semiconductor Corporation

Document Number: 001-06621 Rev. *D

•

198 Champion Court

•

San Jose, CA 95134-1709

•

408-943-2600

Revised March 06, 2008

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Logic Block Diagram (CY7C1148V18)

Write

Reg

Write

Reg

(18:0)

Address

Output

Logic

Control

CLK

Gen.

R/W

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

R/W

[17:0]

BWS

[1:0]

QVLD

Logic Block Diagram (CY7C1150V18)

Write

Reg

Write

Reg

(17:0)

Address

Output

Logic

Control

CLK

Gen.

R/W

DOFF

Read Data Reg.

REF

Reg.

Control

Logic

R/W

[35:0]

BWS

[3:0]

QVLD

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CY7C1148V18, CY7C1150V18

Pin Configurations

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1146V18 (2M x 8)

NC/36M

DQ3

NC/72M

NC/144M

R/W

NWS₁

NC/288M

NWS₀

V_SS

DQ4

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

DQ2

V_DD

V_SS

DQ5

V_DDQ

V_REF

V_DDQ

V_REF

DQ1

DOFF

DQ0

DQ6

V_SS

DQ7

QVLD

TDO

TCK

TMS

TDI

CY7C1157V18 (2M x 9)

NC/144M

BWS₀

NC/36M

DQ3

NC/72M

R/W

NC/288M

V_SS

DQ4

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

DQ2

V_DD

V_SS

DQ5

V_DDQ

V_REF

V_DDQ

V_REF

DQ1

DOFF

DQ0

DQ6

V_SS

DQ7

QVLD

DQ8

TDO

TCK

TMS

TDI

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Pin Configurations (continued)

165-Ball FBGA (13 x 15 x 1.4 mm) Pinout

CY7C1148V18 (1M x 18)

NC/36M

DQ8

NC/72M

NC/144M

R/W

BWS₁

NC/288M

DQ9

DQ7

BWS₀

V_SS

DQ10

V_SS

DQ12

DQ11

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

DQ6

V_DD

V_SS

DQ5

DQ13

V_DDQ

V_REF

V_DDQ

V_REF

DQ4

DOFF

DQ14

DQ3

DQ2

DQ15

V_SS

DQ1

DQ16

DQ17

QVLD

DQ0

TDO

TCK

TMS

TDI

CY7C1150V18 (512K x 36)

NC/72M

NC/144M NC/36M

R/W

BWS₂

BWS₃

BWS₁

BWS₀

DQ27

DQ18

DQ28

DQ19

DQ17

DQ8

DQ7

DQ16

V_SS

DQ29

V_SS

DQ30

DQ31

V_REF

DQ20

DQ21

DQ22

V_DDQ

DQ32

DQ23

DQ24

V_DDQ

V_SS

V_DD

V_SS

V_DDQ

DQ15

DQ6

V_DD

V_SS

DQ5

DQ14

V_DDQ

V_REF

DQ13

DQ12

DOFF

DQ4

DQ3

DQ2

DQ33

DQ35

DQ34

DQ25

DQ26

V_SS

DQ11

DQ1

DQ10

DQ0

QVLD

DQ9

TDO

TCK

TMS

TDI

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Pin Definitions

Pin Name

Pin Description

Input Output- Data Input Output Signals. Inputs are sampled on the rising edge of K and K clocks when write

Synchronous operations are valid. These pins drive out the requested data when a read operation is active. Valid

data is driven out on the rising edge of both the K and K clocks when read operations are active.

[x:0]

When read access is deselected, Q

are automatically tri-stated.

[x:0]

CY7C1146V18 − DQ

[7:0]

CY7C1157V18 − DQ

[8:0]

CY7C1148V18 − DQ

CY7C1150V18 − DQ

[17:0]

[35:0]

Input-

Synchronous Load. This input is brought LOW when a bus cycle sequence is to be defined. This

Synchronous definition includes address and read/write direction. All transactions operate on a burst of two data.

LD must meet the setup and hold times around edge of K.

Input-

Synchronous and K clocks when the write operation is active. It is used to select the nibble that is written into the

device NWS controls D and NWS controls D

Nibble Write Select 0, 1 − Active LOW.(CY7C1146V18 Only) Sampled on the rising edge of the K

NWS , NWS

[7:4]

[3:0]

All the Nibble Write Selects are sampled on the same edge as the data. Deselecting a Nibble Write

Select causes the corresponding nibble of data to be ignored and not written into the device.

BWS , BWS ,

Input-

Byte Write Select 0, 1, 2, and 3 − Active LOW. Sampled on the rising edge of the K and K clocks

BWS , BWS

Synchronous when the Write operation is active. It is used to select the byte that is written into the device when

the current portion of the write operation is active. Bytes not written remain unaltered.

CY7C1157V18 − BWS controls D

[8:0]

CY7C1148V18 − BWS controls D

, and BWS controls D

[17:9].

, BWS controls D

CY7C1148V18 − BWS controls D

, BWS controls D

, and BWS

[26:18] 3

[17:9]

controls D

[35:27]

All the Byte Write Selects are sampled on the same edge as the data. Deselecting a Byte Write Select

causes the corresponding byte of data to be ignored and not written into the device.

Input-

Address Inputs. Sampled on the rising edge of the K clock during active read and write operations.

Synchronous These address inputs are multiplexed for both read and write operations. Internally, the device is

organized as 2M x 8 (two arrays each of1M x 8) for CY7C1146V18, 2M x 9 (two arrays each of 1M

x 9) for CY7C1157V18, 1M x 18 (two arrays each of 512K x 18) for CY7C1148V18, and 512K x 36

(two arrays each of 256K x 18) for CY7C1150V18. All the address inputs are ignored when the

appropriate port is deselected.

R/W

Input-

Synchronous Read/Write Input. When LD is LOW, this input designates the access type (read

Synchronous when R/W is HIGH, write when R/W is LOW) for loaded address. R/W must meet the setup and hold

times around edge of K.

QVLD

Valid Output Valid Output Indicator. The Q Valid indicates valid output data. QVLD is edge aligned with CQ and

Indicator

CQ.

Input-

Clock

Positive Input Clock Input. The rising edge of K is used to capture synchronous inputs to the device

and to drive out data through Q

when in single clock mode. All accesses are initiated on the rising

[x:0]

edge of K.

Input-

Clock

Negative Input Clock Input. K is used to capture synchronous inputs being presented to the device

and to drive out data through Q when in single clock mode.

[x:0]

Clock Output Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 22.

Synchronous Echo Clock Outputs. This is a free running clock and is synchronized to the input

clock (K) of the DDR-II+. The timings for the echo clocks are shown in the “Switching Characteristics”

on page 22.

Clock Output

Input

Output Impedance Matching Input. This input is used to tune the device outputs to the system data

bus impedance. CQ, CQ, and Q

output impedance are set to 0.2 x RQ, where RQ is a resistor

[x:0]

connected between ZQ and ground. Alternatively, connect this pin directly to V

, which enables

DDQ

the minimum impedance mode. This pin cannot be connected directly to GND or left unconnected.

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CY7C1148V18, CY7C1150V18

Pin Definitions (continued)

Pin Name

DOFF

Pin Description

Input

DLL Turn Off − Active LOW. Connecting this pin to ground turns off the DLL inside the device. The

timings in the DLL turned off operation are different from those listed in this data sheet. For normal

operation, connect this pin to a pull up through a 10 KΩ or less pull up resistor. The device behaves

in DDR-I mode when the DLL is turned off. In this mode, operate the device at a frequency of up to

167 MHz with DDR-I timing.

TDO

Output

Input

N/A

TDO for JTAG.

TCK

TCK Pin for JTAG.

TDI

TDI Pin for JTAG.

TMS

TMS Pin for JTAG.

Not Connected to the Die. Tie to any voltage level.

Reference Voltage Input. Static input used to set the reference level for HSTL inputs, Outputs, and

NC/36M

NC/72M

NC/144M

NC/288M

N/A

Input-

REF

Reference AC measurement points.

Power Supply Power Supply Inputs to the Core of the Device.

Ground

Ground for the Device.

Power Supply Power Supply Inputs for the Outputs of the Device.

DDQ

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CY7C1148V18, CY7C1150V18

Byte Write Operations

Functional Overview

Byte Write operations are supported by the CY7C1148V18. A

write operation is initiated as described in the Write Operations.

The CY7C1146V18, CY7C1157V18, CY7C1148V18, and

CY7C1150V18 are synchronous pipelined Burst SRAMs

equipped with a DDR interface.

The bytes that are written are determined by BWS and BWS

which are sampled with each set of 18-bit data word. Asserting

the appropriate Byte Write Select input when the data portion of

a write enables the data presented to be latched and written into

the device. Deasserting the Byte Write Select input when the

data portion of a write enables the data stored in the device for

that byte to remain unaltered. Use this feature to simplify

read/modify/write operations to a Byte Write operation.

Accesses are initiated on the rising edge of the positive input

clock (K). All synchronous input and output timings refer to the

rising edge of the Input clocks (K/K).

All synchronous data inputs (D

) pass through input registers

[x:0]

controlled by the rising edge of the input clocks (K/K). All

synchronous data outputs (Q ) pass through output registers

[x:0]

controlled by the rising edge of the input clocks (K/K) as well.

Double Data Rate Operation

All synchronous control (R/W, LD, BWS ) inputs pass through

[0:X]

The CY7C1148V18 enables high-performance operation

through high clock frequencies (achieved through pipelining) and

double data rate mode of operation. The CY7C1148V18 requires

two No Operation (NOP) cycle when transitioning from a read to

a write cycle. At higher frequencies, some applications may

require a third NOP cycle to avoid contention.

input registers controlled by the rising edge of the input clock (K).

CY7C1148V18 is described in the following sections. The same

basic descriptions apply to CY7C1146V18, CY7C1157V18, and

CY7C1150V18.

Read Operations

If a read occurs after a write cycle, address and data for the write

are stored in registers. The write information must be stored

because the SRAM cannot perform the last word write to the

array without conflicting with the read. The data stays in this

after the read(s), the stored data from the earlier write is written

into the SRAM array. This is called a Posted Write.

The CY7C1148V18 is organized internally as a single array of

1M x 18. Accesses are completed in a burst of two sequential

18-bit data words. Read operations are initiated by asserting

R/W HIGH and LD LOW at the rising edge of the positive input

clock (K). The address presented to Address inputs are stored in

the read address register. Following the next two K clock rise the

corresponding 18-bit word of data from this address location is

If a Read is performed on the same address on which a write is

performed in the previous cycle, the SRAM reads out the most

current data. The SRAM does this by bypassing the memory

array and reading the data from the registers.

driven onto the Q

using K as the output timing reference. On

[17:0]

the subsequent rising edge of K the next 18-bit data word from

the address location generated by the burst counter is driven

onto the Q

. The requested data is valid 0.45 ns from the

[17:0]

rising edge of the input clock (K/K). To maintain the internal logic,

each read access must be enabled to complete. Initiate read

accesses on every rising edge of the positive input clock (K).

Depth Expansion

Depth expansion requires replicating the LD control signal for

each bank. All other control signals can be common between

banks as appropriate.

When read access is deselected, the CY7C1148V18 first

completes the pending read transactions. Synchronous internal

circuitry automatically tri-states the outputs following the next

rising edge of the positive Input clock (K). This enables a

seamless transition between devices without the insertion of wait

states in a depth expanded memory.

Programmable Impedance

An external resistor, RQ, must be connected between the ZQ pin

on the SRAM and V to allow the SRAM to adjust its output

driver impedance. The value of RQ must be 5x the value of the

intended line impedance driven by the SRAM. The allowable

range of RQ to guarantee impedance matching with a tolerance

of ±15% is between 175Ω and 350Ω, with V

output impedance is adjusted every 1024 cycles upon power up

to account for drifts in supply voltage and temperature.

Write Operations

Write operations are initiated by asserting R/W LOW and LD

LOW at the rising edge of the positive input clock (K). The

address presented to Address inputs is stored in the write

address register. On the following K clock rise the data presented

= 1.5V. The

DDQ

to D

provided BWS

is latched and stored into the 18-bit Write Data register

[17:0]

Echo Clocks

are both asserted active. On the subsequent

[1:0]

Echo clocks are provided on the DDR-II+ to simplify data capture

on high-speed systems. Two echo clocks are generated by the

DDR-II+. CQ is referenced with respect to K and CQ is refer-

enced with respect to K. These are free-running clocks and are

synchronized to the Input clock of the DDR-II+. The timings for

the echo clocks are shown in the “Switching Characteristics” on

page 22.

rising edge of the Negative Input Clock (K) the information

presented to D is also stored into the Write Data register

[17:0]

provided BWS

are both asserted active. The 36 bits of data

[1:0]

is then written into the memory array at the specified location.

Initiate write accesses on every rising edge of the positive input

clock (K). This pipelines the data flow such that 18 bits of data

transfers into the device on every rising edge of the input clocks

(K and K).

Valid Data Indicator (QVLD)

When write access is deselected, the device ignores all inputs

after the pending write operations are completed.

QVLD is provided on the DDR-II+ to simplify data capture on high

speed systems. The QVLD is generated by the DDR-II+ device

along with Data output. This signal is also edge-aligned with the

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

echo clock and follows the timing of any data pin. This signal is

asserted half a cycle before valid data arrives.

DDR-I mode (with 1.0 cycle latency and a longer access time).

For more information, refer to the application note, “DLL Consid-

erations in QDRII/DDRII/QDRII+/DDRII+”. The DLL can also be

reset by slowing or stopping the input clocks K and K for a

minimum of 30 ns. However, it is not necessary for the DLL to be

reset in order to lock to the desired frequency. During Power up,

when the DOFF is tied HIGH, the DLL gets locked after 2048

cycles of stable clock.

DLL

These chips utilize a Delay Lock Loop (DLL) that is designed to

function between 120 MHz and the specified maximum clock

frequency. The DLL may be disabled by applying ground to the

DOFF pin. When the DLL is turned off, the device behaves in

Application Example

Figure 1 shows two DDR-II+ used in an application.

Figure 1. Application Example

CQ/CQ

SRAM#1

LD R/W

SRAM#2

R = 250ohms

LD R/W

Addresses

Cycle Start

R/W

Source CLK

BUS

MASTER

(CPU or ASIC)

Echo Clock1/Echo Clock1

Echo Clock2/Echo Clock2

Truth Table

[3 , 4, 5, 6, 7, 8]

The truth table for the CY7C1146V18, CY7C1157V18, CY7C1148V18, and CY7C1150V18 follows.

Operation

LD R/W

Write Cycle:

L – H

D(A) at K (t + 1) ↑

D(A + 1) at K (t + 1) ↑

Load address; wait one cycle; input write data on consecutive

K and K rising edges.

Read Cycle: (2.0 cycle latency)

Load address; wait two cycle; read data on consecutive K and

K rising edges.

L – H

Q(A) at K (t + 2)↑

Q(A + 1) at K (t + 2) ↑

NOP: No Operation

L – H

High-Z

Standby: Clock Stopped

Stopped

Previous State

Notes

2. The above application shows two DDR-II+ used.

^{3. X = “Don’t Care,” H = Logic HIGH, L = Logic LOW,}↑ represents rising edge.

4. Device powers up deselected and the outputs in a tri-state condition.

5. “A” represents address location latched by the devices when transaction was initiated and A + 1 represents the addresses sequence in the burst.

6. “t” represents the cycle at which a Read/Write operation is started. t + 1 and t + 2 are the first and second clock cycles succeeding the “t” clock cycle.

7. Data inputs are registered at K and K rising edges. Data outputs are delivered on K and K rising edges.

8. It is recommended that K = K = HIGH when clock is stopped. This is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically.

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CY7C1148V18, CY7C1150V18

Write Cycle Descriptions

[3, 9]

The write cycle descriptions of CY7C1146V18 and CY7C1148V18 follows.

BWS / BWS /

Comments

NWS

L – H

–

When the Data portion of a write sequence is active:

CY7C1146V18 − both nibbles (D

) are written into the device.

[7:0]

CY7C1148V18 − both bytes (D

) are written into the device.

[17:0]

–

L – H

–

L – H When the Data portion of a write sequence is active:

CY7C1146V18 − both nibbles (D

) are written into the device.

[7:0]

CY7C1148V18 − both bytes (D

[17:0]

–

When the Data portion of a write sequence is active:

CY7C1146V18 − only the lower nibble (D

) is written into the device, D

remains unaltered.

[3:0]

[7:4]

CY7C1148V18 − only the lower byte (D

[8:0]

[17:9]

L – H When the Data portion of a write sequence is active:

CY7C1146V18 − only the lower nibble (D

) is written into the device, D

remains unaltered.

[3:0]

[7:4]

CY7C1148V18 − only the lower byte (D

[8:0]

[17:9]

L – H

–

When the Data portion of a write sequence is active:

CY7C1146V18 − only the upper nibble (D

) is written into the device, D

remains unaltered.

[7:4]

[3:0]

[8:0]

CY7C1148V18 − only the upper byte (D

[17:9]

L – H When the Data portion of a write sequence is active:

CY7C1146V18 − only the upper nibble (D

) is written into the device, D

remains unaltered.

[7:4]

[3:0]

[8:0]

CY7C1148V18 − only the upper byte (D

[17:9]

L – H

–

No data is written into the devices when this portion of a write operation is active.

L – H No data is written into the devices when this portion of a write operation is active.

[3, 9]

The write cycle descriptions of CY7C1146V18 follows.

BWS

L – H

–

Comments

–

When the Data portion of a write sequence is active, the single byte (D

) is written into the device.

[8:0]

L – H When the Data portion of a write sequence is active, the single byte (D

[8:0]

L – H

–

No data is written into the device when this portion of a write operation is active.

L – H No data is written into the device when this portion of a write operation is active.

Note

9. Is based on a Write cycle was initiated in accordance with the Write Cycle Description Truth Table. Alter BWS , BWS , BWS , and BWS on different portions of a Write

cycle, as long as the setup and hold requirements are achieved.

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CY7C1148V18, CY7C1150V18

[3, 9]

The write cycle descriptions of CY7C1148V18 follows,

BWS

Comments

L – H

–

When the Data portion of a write sequence is active, all four bytes (D

written into the device.

) are

[35:0]

–

L – H

–

L – H When the Data portion of a write sequence is active, all four bytes (D

written into the device.

[35:0]

–

When the Data portion of a write sequence is active, only the lower byte (D

) is

[8:0]

written into the device. D

remains unaltered.

[35:9]

L – H When the Data portion of a write sequence is active, only the lower byte (D

written into the device. D remains unaltered.

[35:9]

L – H

–

When the Data portion of a write sequence is active, only the byte (D

) is written

[17:9]

into the device. D

and D

remains unaltered.

[8:0]

[35:18]

L – H When the Data portion of a write sequence is active, only the byte (D

into the device. D and D remains unaltered.

) is written

[17:9]

[8:0]

[35:18]

L – H

–

When the Data portion of a write sequence is active, only the byte (D

) is

[26:18]

written into the device. D

and D

remains unaltered.

[17:0]

[35:27]

L – H When the Data portion of a Write sequence is active, only the byte (D

) is

[26:18]

written into the device. D

and D

remains unaltered.

[17:0]

[35:27]

L – H

–

When the Data portion of a write sequence is active, only the byte (D

) is

[35:27]

written into the device. D

remains unaltered.

[26:0]

L – H When the Data portion of a write sequence is active, only the byte (D

written into the device. D remains unaltered.

[26:0]

L – H

–

No data is written into the device when this portion of a write operation is active.

L – H No data is written into the device when this portion of a write operation is active.

Document Number: 001-06621 Rev. *D

Page 11 of 27

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CY7C1146V18, CY7C1157V18

CY7C1148V18, CY7C1150V18

Instruction Register

IEEE 1149.1 Serial Boundary Scan (JTAG)

Serially load three-bit instructions into the instruction register.

This register is loaded when it is placed between the TDI and

TDO pins as shown in “TAP Controller Block Diagram” on

page 15. Upon power up, the instruction register is loaded with

the IDCODE instruction. It is also loaded with the IDCODE

instruction if the controller is placed in a reset state as described

in the previous section.

These SRAMs incorporate a serial boundary scan test access

port (TAP) in the FBGA package. This part is fully compliant with

IEEE Standard 1149.1-2001. The TAP operates using JEDEC

standard 1.8V IO logic levels.

Disabling the JTAG Feature

It is possible to operate the SRAM without using the JTAG

feature. To disable the TAP controller, TCK must be tied LOW

When the TAP controller is in the Capture IR state, the two least

significant bits are loaded with a binary “01” pattern to allow for

fault isolation of the board level serial test path.

(V ) to prevent clocking of the device. TDI and TMS are inter-

nally pulled up and may be unconnected. They may alternately

be connected to V through a pull up resistor. TDO must be left

unconnected. Upon power up, the device comes up in a reset

state which does not interfere with the operation of the device.

Bypass Register

To save time when serially shifting data through registers, it is

sometimes advantageous to skip certain chips. The bypass

and TDO pins. This allows data to be shifted through the SRAM

with minimal delay. The bypass register is set LOW (V ) when

the BYPASS instruction is executed.

Test Access Port—Test Clock

The test clock is used only with the TAP controller. All inputs are

captured on the rising edge of TCK. All outputs are driven from

the falling edge of TCK.

Boundary Scan Register

Test Mode Select

The boundary scan register is connected to all of the input and

output pins on the SRAM. Several no connect (NC) pins are also

included in the scan register to reserve pins for higher density

devices.

The TMS input is used to give commands to the TAP controller

and is sampled on the rising edge of TCK. It is allowable to leave

this pin unconnected if the TAP is not used. The pin is pulled up

internally, resulting in a logic HIGH level.

The boundary scan register is loaded with the contents of the

RAM Input and Output ring when the TAP controller is in the

Capture-DR state and is then placed between the TDI and TDO

pins when the controller is moved to the Shift-DR state. Use the

EXTEST, SAMPLE/PRELOAD, and SAMPLE Z instructions to

capture the contents of the Input and Output ring.

Test Data-In (TDI)

The TDI pin is used to serially input information into the registers

and connect to the input of any of the registers. The register

between TDI and TDO is chosen by the instruction that is loaded

into the TAP instruction register. For more information on loading

the instruction register, see the “TAP Controller State Diagram”

on page 14. TDI is internally pulled up and unconnected if the

TAP is unused in an application. TDI is connected to the most

significant bit (MSb) on any register.

The “Boundary Scan Order” on page 18 show the order in which

the bits are connected. Each bit corresponds to one of the bumps

on the SRAM package. The MSb of the register is connected to

TDI, and the LSb is connected to TDO.

Identification (ID) Register

Test Data-Out (TDO)

The ID register is loaded with a vendor-specific, 32-bit code

during the Capture-DR state when the IDCODE command is

loaded in the instruction register. The IDCODE is hardwired into

the SRAM and can be shifted out when the TAP controller is in

the Shift-DR state. The ID register has a vendor code and other

information described in the “Identification Register Definitions”

on page 17.

The TDO output pin is used to serially clock data out from the

registers. The output is active depending upon the current state

of the TAP state machine (see Instruction codes). The output

changes on the falling edge of TCK. TDO is connected to the

least significant bit (LSB) of any register.

Performing a TAP Reset

A Reset is performed by forcing TMS HIGH (V ) for five rising

TAP Instruction Set

edges of TCK. This RESET does not affect the operation of the

SRAM and may be performed while the SRAM is operating. At

power up, the TAP is reset internally to ensure that TDO comes

up in a High-Z state.

Eight different instructions are possible with the three-bit

instruction register. All combinations are listed in the Instruction

Code table. Three of these instructions are listed as RESERVED

and must not be used. The other five instructions are described

in detail in the following section.

TAP Registers

Instructions are loaded into the TAP controller during the Shift-IR

state when the instruction register is placed between TDI and

TDO. When this state is active, instructions are shifted through

the instruction register through the TDI and TDO pins. To

execute the instruction after it is shifted in, the TAP controller

needs to be moved into the Update-IR state.

Registers are connected between the TDI and TDO pins and

allow data to be scanned into and out of the SRAM test circuitry.

Select only one register at a time through the instruction

registers. Data is serially loaded into the TDI pin on the rising

edge of TCK. Data is output on the TDO pin on the falling edge

of TCK.

Document Number: 001-06621 Rev. *D

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CY7C1148V18, CY7C1150V18

IDCODE

PRELOAD enables an initial data pattern to be placed at the

latched parallel outputs of the boundary scan register cells be-

fore the selection of another boundary scan test operation.

The IDCODE instruction causes a vendor-specific, 32-bit code

to be loaded into the instruction register. It also places the

instruction register between the TDI and TDO pins and enables

the IDCODE to be shifted out of the device when the TAP

controller enters the Shift-DR state. The IDCODE instruction is

loaded into the instruction register upon power up or whenever

the TAP controller is supplied a test logic reset state.

The shifting of data for the SAMPLE and PRELOAD phases can

occur concurrently when required — that is, while data captured

is shifted out, shift in the preloaded data.

BYPASS

When the BYPASS instruction is loaded in the instruction register

and the TAP is placed in a Shift-DR state, the bypass register is

placed between the TDI and TDO pins. The advantage of the

BYPASS instruction is that it shortens the boundary scan path

when multiple devices are connected together on a board.

SAMPLE Z

The SAMPLE Z instruction causes the boundary scan register to

be connected between the TDI and TDO pins when the TAP

controller is in a Shift-DR state. The SAMPLE Z command puts

the output bus into a High-Z state until the next command is

supplied when the Update IR state is active.

EXTEST

The EXTEST instruction enables the preloaded data to be driven

out through the system output pins. This instruction also selects

the boundary scan register to be connected for serial access

between the TDI and TDO in the shift-DR controller state.

SAMPLE/PRELOAD

SAMPLE/PRELOAD is a 1149.1 mandatory instruction. When

the SAMPLE/PRELOAD instructions are loaded into the instruc-

tion register and the TAP controller is in the Capture-DR state, a

snapshot of data on the inputs and output pins is captured in the

boundary scan register.

EXTEST Output Bus Tri-State

IEEE Standard 1149.1 mandates that the TAP controller be able

to put the output bus into a tri-state mode.

The user must be aware that the TAP controller clock can only

operate at a frequency up to 20 MHz, while the SRAM clock

operates more than an order of magnitude faster. Because there

is a large difference in the clock frequencies, it is possible that

when the Capture-DR state is active, an input or output under-

goes a transition. The TAP may then try to capture a signal while

in transition (metastable state). This does not harm the device,

but there is no guarantee as to the value that is captured. Re-

peatable results may not be possible.

The boundary scan register has a special bit located at bit 47.

When this scan cell, called the “extest output bus tri-state”, is

latched into the preload register the Update-DR state in the TAP

controller, it directly controls the state of the output (Q-bus) pins,

when the EXTEST is entered as the current instruction. When

HIGH, it enables the output buffers to drive the output bus. When

LOW, this bit places the output bus into a High-Z condition.

Set this bit by entering the SAMPLE/PRELOAD or EXTEST

command, and then shifting the desired bit into that cell, when

the Shift-DR state is active. When the Update-DR is active, the

value loaded into that shift-register cell latches into the preload

controls the output Q-bus pins. Note that this bit is preset HIGH

to enable the output when the device is powered up, and also

when the TAP controller is in the Test-Logic-Reset state.

To guarantee that the boundary scan register captures the cor-

rect value of a signal, the SRAM signal must be stabilized long

enough to meet the TAP controller's capture setup plus hold

times (t and t ). The SRAM clock input might not be captured

correctly if there is no way in a design to stop (or slow) the clock

a SAMPLE/PRELOAD instruction. If this is an issue, it is still

possible to capture all other signals and simply ignore the value

of the CK and CK captured in the boundary scan register.

Reserved

After the data is captured, it is possible to shift out the data by

putting the TAP into the Shift-DR state. This places the boundary

scan register between the TDI and TDO pins.

These instructions are not implemented but are reserved for

future use. Do not use these instructions.

Document Number: 001-06621 Rev. *D

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