PRELIMINARY
CY14B102L, CY14B102N
2 Mbit (256K x 8/128K x 16) nvSRAM
Features
Functional Description
■ 20 ns, 25 ns, and 45 ns Access Times
The Cypress CY14B102L/CY14B102N is a fast static RAM, with
a nonvolatile element in each memory cell. The memory is
■ Internally organized as 256K x 8 (CY14B102L) or 128K x 16
(CY14B102N)
organized as 256K bytes of 8 bits each or 128K words of 16 bits
each. The embedded nonvolatile elements incorporate
QuantumTrap technology, producing the world’s most reliable
nonvolatile memory. The SRAM provides infinite read and write
cycles, while independent nonvolatile data resides in the highly
reliable QuantumTrap cell. Data transfers from the SRAM to the
nonvolatile elements (the STORE operation) takes place
automatically at power down. On power up, data is restored to
the SRAM (the RECALL operation) from the nonvolatile memory.
Both the STORE and RECALL operations are also available
under software control.
■ Hands off Automatic STORE on power down with only a small
Capacitor
®
■ STORE to QuantumTrap nonvolatile elements initiated by
®
software, device pin, or AutoStore on power down
■ RECALL to SRAM initiated by software or power up
■ Infinite Read, Write, and Recall Cycles
■ 200,000 STORE cycles to QuantumTrap
■ 20 year data retention
■ Single 3V +20% to -10% operation
■ Commercial, Industrial and Automotive Temperatures
■ 48-ball FBGA and 44/54-pin TSOP - II packages
■ Pb-free and RoHS compliance
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Note
1. Address A - A for x8 configuration and Address A - A for x16 configuration.
0
17
0
16
2. Data DQ - DQ for x8 configuration and Data DQ - DQ for x16 configuration.
0
7
0
15
3. BHE and BLE are applicable for x16 configuration only.
Cypress Semiconductor Corporation
Document #: 001-45754 Rev. *B
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised November 10, 2008
PRELIMINARY
CY14B102L, CY14B102N
Pinouts (continued)
Figure 3. Pin Diagram - 54 Pin TSOP II (x16)
[6]
NC
A
0
54
53
52
51
50
49
HSB
1
2
3
NC
NC
A
A
1
4
16
A
2
A
15
OE
5
A
3
6
48
47
46
45
A
BHE
7
8
9
10
11
12
13
14
4
CE
DQ0
DQ1
BLE
DQ15
DQ14
DQ13
DQ12
(x16)
DQ2
DQ3
44
43
42
41
40
39
(Not to Scale)
V
CC
V
SS
V
SS
V
CC
DQ4
DQ5
DQ11
DQ10
DQ9
15
16
17
18
19
20
21
22
23
24
38
37
36
35
DQ6
DQ7
WE
DQ8
V
CAP
A
5
A
14
34
33
32
31
30
29
28
A
6
A
13
A
A
7
A
8
12
A
11
A
10
A
9
NC
NC
NC
25
26
27
NC
NC
NC
Pin Definitions
Pin Name
IO Type
Description
A – A
Input
Address Inputs Used to Select one of the 262,144 bytes of the nvSRAM for x8 Configuration.
Address Inputs Used to Select one of the 131,072 words of the nvSRAM for x16 Configuration.
0
17
16
A – A
0
DQ – DQ
Input/Output Bidirectional Data IO Lines for x8 Configuration. Used as input or output lines depending on
0
7
operation.
DQ – DQ
Bidirectional Data IO Lines for x16 Configuration. Used as input or output lines depending on
0
15
operation.
WE
Input
Write Enable Input, Active LOW. When selected LOW, data on the IO pins is written to the specific
address location.
Input
Input
Chip Enable Input, Active LOW. When LOW, selects the chip. When HIGH, deselects the chip.
CE
OE
Output Enable, Active LOW. The active LOW OE input enables the data output buffers during read
cycles. IO pins are tri-stated on deasserting OE HIGH.
Input
Input
Byte High Enable, Active LOW. Controls DQ - DQ .
BHE
BLE
15
8
Byte Low Enable, Active LOW. Controls DQ - DQ .
7
0
V
Ground
Ground for the Device. Must be connected to the ground of the system.
SS
V
Power Supply Power Supply Inputs to the Device.
CC
Input/Output Hardware Store Busy (HSB). When LOW this output indicates that a hardware store is in progress.
When pulled LOW external to the chip it initiates a nonvolatile STORE operation. A weak internal pull
up resistor keeps this pin HIGH if not connected (connection optional). After each store operation HSB
will be driven HIGH for short time with standard output high current.
HSB
V
Power Supply AutoStore Capacitor. Supplies power to the nvSRAM during power loss to store data from SRAM to
CAP
nonvolatile elements.
NC
No Connect No Connect. This pin is not connected to the die.
Document #: 001-45754 Rev. *B
Page 3 of 24
PRELIMINARY
CY14B102L, CY14B102N
Figure 4 shows the proper connection of the storage capacitor
Device Operation
CAP
The CY14B102L/CY14B102N nvSRAM is made up of two
functional components paired in the same physical cell. They are
an SRAM memory cell and a nonvolatile QuantumTrap cell. The
SRAM memory cell operates as a standard fast static RAM. Data
in the SRAM is transferred to the nonvolatile cell (the STORE
operation), or from the nonvolatile cell to the SRAM (the RECALL
operation). Using this unique architecture, all cells are stored and
recalled in parallel. During the STORE and RECALL operations,
SRAM read and write operations are inhibited. The
CY14B102L/CY14B102N supports infinite reads and writes
similar to a typical SRAM. In addition, it provides infinite RECALL
operations from the nonvolatile cells and up to 200K STORE
page 15 for a complete description of read and write modes.
CAP
CAP
CC
up should be placed on WE to hold it inactive during power up.
This pull up is only effective if the WE signal is tri-state during
power up. Many MPUs tri-state their controls on power up. This
should be verified when using the pull up. When the nvSRAM
comes out of power-on-recall, the MPU must be active or the WE
held inactive until the MPU comes out of reset.
To reduce unnecessary nonvolatile stores, AutoStore and
hardware store operations are ignored unless at least one write
operation has taken place since the most recent STORE or
RECALL cycle. Software initiated STORE cycles are performed
regardless of whether a write operation has taken place. The
HSB signal is monitored by the system to detect if an AutoStore
cycle is in progress.
SRAM Read
Figure 4. AutoStore Mode
The CY14B102L/CY14B102N performs a read cycle when CE
and OE are LOW and WE and HSB are HIGH. The address
Vcc
specified on pins A
or A
determines which of the 262,144
0-17
0-16
data bytes or 131,072 words of 16 bits each are accessed. Byte
enables (BHE, BLE) determine which bytes are enabled to the
output, in the case of 16-bit words. When the read is initiated by
0.1uF
an address transition, the outputs are valid after a delay of t
Vcc
AA
(read cycle 1). If the read is initiated by CE or OE, the outputs
are valid at t or at t , whichever is later (read cycle 2). The
ACE
DOE
data output repeatedly responds to address changes within the
access time without the need for transitions on any control
WE
VCAP
t
AA
input pins. This remains valid until another address change or
until CE or OE is brought HIGH, or WE or HSB is brought LOW.
VCAP
VSS
SRAM Write
A write cycle is performed when CE and WE are LOW and HSB
is HIGH. The address inputs must be stable before entering the
write cycle and must remain stable until CE or WE goes HIGH at
Hardware STORE Operation
the end of the cycle. The data on the common IO pins DQ
0–15
[7]
are written into the memory if the data is valid t before the end
The CY14B102L/CY14B102N provides the HSB pin to control
and acknowledge the STORE operations. Use the HSB pin to
request a hardware STORE cycle. When the HSB pin is driven
LOW, the CY14B102L/CY14B102N conditionally initiates a
SD
of a WE controlled write or before the end of an CE controlled
write. The Byte Enable inputs (BHE, BLE) determine which bytes
are written, in the case of 16-bit words. It is recommended that
OE be kept HIGH during the entire write cycle to avoid data bus
contention on common IO lines. If OE is left LOW, internal
STORE operation after t
. An actual STORE cycle only
DELAY
begins if a write to the SRAM has taken place since the last
STORE or RECALL cycle. The HSB pin also acts as an open
drain driver that is internally driven LOW to indicate a busy
condition when the STORE (initiated by any means) is in
progress.
circuitry turns off the output buffers t
after WE goes LOW.
HZWE
AutoStore Operation
SRAM read and write operations that are in progress when HSB
is driven LOW by any means are given time to complete before
the STORE operation is initiated. After HSB goes LOW, the
CY14B102L/CY14B102N continues SRAM operations for
The CY14B102L/CY14B102N stores data to the nvSRAM using
one of the following three storage operations: Hardware Store
activated by HSB; Software Store activated by an address
sequence; AutoStore on device power down. The AutoStore
operation is a unique feature of QuantumTrap technology and is
enabled by default on the CY14B102L/CY14B102N.
t
. If a write is in progress when HSB is pulled LOW it is
DELAY
enabled a time, t
to complete. However, any SRAM write
DELAY
cycles requested after HSB goes LOW are inhibited until HSB
returns HIGH. In case the write latch is not set, HSB will not be
driven LOW by the CY14B102L/CY14B102N but any SRAM
read and write cycles are inhibited until HSB is returned HIGH by
MPU or other external source.
During a normal operation, the device draws current from V to
CC
charge a capacitor connected to the V
pin. This stored
CAP
charge is used by the chip to perform a single STORE operation.
If the voltage on the V pin drops below V , the part
CC
SWITCH
automatically disconnects the V
pin from V . A STORE
CAP
CC
During any STORE operation, regardless of how it is initiated,
the CY14B102L/CY14B102N continues to drive the HSB pin
LOW, releasing it only when the STORE is complete. Upon
operation is initiated with power provided by the V
capacitor.
CAP
Document #: 001-45754 Rev. *B
Page 4 of 24
PRELIMINARY
CY14B102L, CY14B102N
completion
of
the
STORE
operation,
the
The software sequence may be clocked with CE controlled reads
or OE controlled reads. After the sixth address in the sequence
is entered, the STORE cycle commences and the chip is
disabled. HSB will be driven LOW. It is important to use read
cycles and not write cycles in the sequence, although it is not
necessary that OE be LOW for a valid sequence. After the
CY14B102L/CY14B102N remains disabled until the HSB pin
returns HIGH. Leave the HSB unconnected if it is not used.
Hardware RECALL (Power Up)
During power up or after any low power condition
t
cycle time is fulfilled, the SRAM is activated again for the
STORE
(V < V
), an internal RECALL request is latched. When
CC
SWITCH
read and write operation.
V
again exceeds the sense voltage of V
, a RECALL
to complete.
CC
SWITCH
cycle is automatically initiated and takes t
HRECALL
Software RECALL
During this time, HSB will be driven LOW by the HSB driver.
Transfer the data from the nonvolatile memory to the SRAM with
a software address sequence. A software RECALL cycle is
initiated with a sequence of read operations in a manner similar
to the software STORE initiation. To initiate the RECALL cycle,
the following sequence of CE controlled read operations must be
performed.
Software STORE
Transfer data from the SRAM to the nonvolatile memory with a
software address sequence. The CY14B102L/CY14B102N
software STORE cycle is initiated by executing sequential CE
controlled read cycles from six specific address locations in
exact order. During the STORE cycle an erase of the previous
nonvolatile data is first performed, followed by a program of the
nonvolatile elements. After a STORE cycle is initiated, further
input and output are disabled until the cycle is completed.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x4C63 Initiate RECALL Cycle
Because a sequence of READs from specific addresses is used
for STORE initiation, it is important that no other read or write
accesses intervene in the sequence, or the sequence is aborted
and no STORE or RECALL takes place.
Internally, RECALL is a two step procedure. First, the SRAM data
is cleared; then, the nonvolatile information is transferred into the
To initiate the software STORE cycle, the following read
sequence must be performed.
SRAM cells. After the t
cycle time, the SRAM is again
RECALL
ready for read and write operations. The RECALL operation
does not alter the data in the nonvolatile elements.
1. Read Address 0x4E38 Valid READ
2. Read Address 0xB1C7 Valid READ
3. Read Address 0x83E0 Valid READ
4. Read Address 0x7C1F Valid READ
5. Read Address 0x703F Valid READ
6. Read Address 0x8FC0 Initiate STORE Cycle
Table 1. Mode Selection
A
- A
X
Mode
IO
Power
Standby
Active
CE
WE
OE, BHE, BLE
15
0
H
X
X
Not Selected
Read SRAM
Write SRAM
Output High Z
Output Data
Input Data
L
L
L
H
L
L
X
L
X
X
Active
H
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8B45
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
Disable
Notes
8. While there are 18 address lines on the CY14B102L (17 address lines on the CY14B102N), only the 13 address lines (A - A ) are used to control software modes.
14
2
Rest of the address lines are don’t care.
9. The six consecutive address locations must be in the order listed. WE must be HIGH during all six cycles to enable a nonvolatile cycle.
10. IO state depends on the state of OE, BHE, and BLE. The IO table shown assumes OE, BHE, and BLE LOW.
Document #: 001-45754 Rev. *B
Page 5 of 24
PRELIMINARY
CY14B102L, CY14B102N
Table 1. Mode Selection (continued)
[8]
[3]
A
- A
Mode
IO
Power
CE
WE
OE, BHE, BLE
15
0
L
H
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4B46
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
AutoStore Enable
Output Data
Output Data
Output Data
Output Data
Output Data
Output Data
Active
L
L
H
H
L
L
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x8FC0
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Output Data
Output Data
Output Data
Output Data
Output Data
Active I
CC2
Nonvolatile Store Output High Z
0x4E38
0xB1C7
0x83E0
0x7C1F
0x703F
0x4C63
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Read SRAM
Nonvolatile
Recall
Output Data
Output Data
Output Data
Output Data
Output Data
Output High Z
Active
If the AutoStore function is disabled or re-enabled, a manual
STORE operation (hardware or software) must be issued to save
the AutoStore state through subsequent power down cycles. The
part comes from the factory with AutoStore enabled.
Preventing AutoStore
The AutoStore function is disabled by initiating an AutoStore
disable sequence. A sequence of read operations is performed
in a manner similar to the software STORE initiation. To initiate
the AutoStore disable sequence, the following sequence of CE
controlled read operations must be performed:
Data Protection
The CY14B102L/CY14B102N protects data from corruption
during low voltage conditions by inhibiting all externally initiated
STORE and write operations. The low voltage condition is
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x8B45 AutoStore Disable
detected when V < V
. If the CY14B102L/CY14B102N
CC
SWITCH
is in a write mode (both CE and WE are LOW) at power up, after
a RECALL or STORE, the write is inhibited until the SRAM is
enabled after t
(HSB to output active). This protects against
LZHSB
inadvertent writes during power up or brown out conditions.
The AutoStore is re-enabled by initiating an AutoStore enable
sequence. A sequence of read operations is performed in a
manner similar to the software RECALL initiation. To initiate the
AutoStore enable sequence, the following sequence of CE
controlled read operations must be performed:
Noise Considerations
1. Read address 0x4E38 Valid READ
2. Read address 0xB1C7 Valid READ
3. Read address 0x83E0 Valid READ
4. Read address 0x7C1F Valid READ
5. Read address 0x703F Valid READ
6. Read address 0x4B46 AutoStore Enable
Document #: 001-45754 Rev. *B
Page 6 of 24
PRELIMINARY
CY14B102L, CY14B102N
Package Power Dissipation
Maximum Ratings
Capability (T = 25°C) ................................................... 1.0W
A
Exceeding maximum ratings may impair the useful life of the
device. These user guidelines are not tested.
Surface Mount Pb Soldering
Temperature (3 Seconds).......................................... +260°C
Storage Temperature ................................. –65°C to +150°C
Maximum Accumulated Storage Time
DC Output Current (1 output at a time, 1s duration).... 15 mA
Static Discharge Voltage.......................................... > 2001V
(per MIL-STD-883, Method 3015)
............At 150°C Ambient Temperature........................1000h
............At 85°C Ambient Temperature..................... 20 Years
Latch Up Current ................................................... > 200 mA
Ambient Temperature with
Power Applied ............................................ –55°C to +150°C
Operating Range
Range
Commercial
Industrial
Ambient Temperature
0°C to +70°C
V
CC
Supply Voltage on V Relative to GND ..........–0.5V to 4.1V
CC
2.7V to 3.6V
2.7V to 3.6V
2.7V to 3.6V
Voltage Applied to Outputs
in High-Z State.......................................–0.5V to V + 0.5V
–40°C to +85°C
–40°C to +125°C
CC
Automotive
Input Voltage...........................................–0.5V to Vcc + 0.5V
Transient Voltage (<20 ns) on
Any Pin to Ground Potential ..................–2.0V to V + 2.0V
CC
DC Electrical Characteristics
Over the Operating Range (V = 2.7V to 3.6V)
CC
Parameter
Description
Average V Current
Test Conditions
Min
Max
Unit
I
t
t
t
= 20 ns
= 25 ns
= 45 ns
Commercial
Industrial
65
65
50
70
70
52
mA
mA
mA
mA
mA
mA
CC1
CC
RC
RC
RC
Values obtained without output loads (I
= 0 mA)
OUT
t
t
= 25 ns
= 45 ns
Automotive
90
75
mA
mA
RC
RC
Values obtained without output loads (I
= 0 mA)
= 0 mA).
OUT
I
I
Average V Current All Inputs Don’t Care, V = Max
Average current for duration t
AverageV Currentat All I/P cycling at CMOS levels.
10
35
mA
mA
CC2
CC
CC
during STORE
STORE
CC3
CC
t
= 200 ns, 3V, 25°C Values obtained without output loads (I
RC
OUT
typical
I
I
Average V
Current All Inputs Don’t Care, V = Max
5
5
mA
mA
CC4
CAP
CC
during AutoStore Cycle Average current for duration t
STORE
V
Standby Current CE > (V – 0.2). All others V < 0.2V or > (V – 0.2V). Standby
SB
CC
CC IN CC
current level after nonvolatile cycle is complete.
Inputs are static. f = 0 MHz.
I
Input Leakage Current V = Max, V < V < V
(except HSB)
Input Leakage Current V = Max, V < V < V
(for HSB)
Off-State Output
Leakage Current
Input HIGH Voltage
–1
–100
–1
+1
+1
+1
μA
μA
μA
V
IX
CC
SS
IN
CC
CC
SS
IN
CC
I
V
= Max, V < V
< V , CE or OE > V or BHE/BLE > V
IH
OZ
CC
SS
OUT
CC
IH
or WE < V
IL
V
2.0
V
+
IH
CC
0.5
V
V
V
V
Input LOW Voltage
Output HIGH Voltage
Output LOW Voltage
Storage Capacitor
V
– 0.5
0.8
V
V
V
IL
ss
I
I
= –2 mA
= 4 mA
2.4
61
OH
OL
OUT
OUT
0.4
180
Between V
pin and V , 5V Rated
μF
CAP
CAP
SS
Notes
11. Typical conditions for the active current shown on the DC Electrical characteristics are average values at 25°C (room temperature), and V = 3V. Not 100% tested.
CC
12. The HSB pin has I
= -2 uA for V of 2.4V when both active HIGH and LOW drivers are disabled. When they are enabled standard V and V are valid. This
OUT
O
H
O
H
O
L
parameter is characterized but not tested.
13. V (Storage capacitor) nominal value is 68uF.
CAP
Document #: 001-45754 Rev. *B
Page 7 of 24
PRELIMINARY
CY14B102L, CY14B102N
Data Retention and Endurance
Parameter
Description
Min
20
Unit
Years
K
DATA
Data Retention
R
NV
Nonvolatile STORE Operations
200
C
Capacitance
In the following table, the capacitance parameters are listed.
Parameter Description
Input Capacitance
Output Capacitance
Test Conditions
Max
7
Unit
C
C
T = 25°C, f = 1 MHz,
pF
pF
IN
A
V
= 0 to 3.0V
CC
7
OUT
Thermal Resistance
In the following table, the thermal resistance parameters are listed.
Parameter
Description
Test Conditions
Test conditions follow standard test methods
48-FBGA 44-TSOP II 54-TSOP II Unit
ΘJA
Thermal Resistance
(Junction to Ambient) and procedures for measuring thermal
28.82
31.11
30.73
°C/W
impedance, in accordance with EIA/JESD51.
ΘJC
Thermal Resistance
(Junction to Case)
7.84
5.56
6.08
°C/W
Figure 5. AC Test Loads
577Ω
R1
for tri-state specs
577Ω
3.0V
OUTPUT
3.0V
OUTPUT
R1
R2
789Ω
R2
789Ω
5 pF
30 pF
AC Test Conditions
Input Pulse Levels.................................................... 0V to 3V
Input Rise and Fall Times (10% - 90%)........................ <3 ns
Input and Output Timing Reference Levels.................... 1.5V
Note
14. These parameters are guaranteed but not tested.
Document #: 001-45754 Rev. *B
Page 8 of 24
PRELIMINARY
CY14B102L, CY14B102N
AC Switching Characteristics
Parameters
20 ns
25 ns
45 ns
Description
Unit
Cypress
Alt
Min
Max
Min
Max
Min
Max
Parameters Parameters
SRAM Read Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Chip Enable Access Time
Read Cycle Time
20
25
45
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ACE
RC
ACS
RC
AA
20
25
45
Address Access Time
20
10
25
12
45
20
AA
Output Enable to Data Valid
Output Hold After Address Change
Chip Enable to Output Active
Chip Disable to Output Inactive
Output Enable to Output Active
Output Disable to Output Inactive
Chip Enable to Power Active
Chip Disable to Power Standby
Byte Enable to Data Valid
DOE
OHA
OE
OH
LZ
3
3
3
3
3
3
LZCE
8
8
10
10
15
15
HZCE
HZ
0
0
0
0
0
0
LZOE
OLZ
OHZ
PA
HZOE
PU
PD
20
10
25
12
45
20
PS
-
-
-
DBE
Byte Enable to Output Active
Byte Disable to Output Inactive
0
0
0
LZBE
HZBE
8
10
15
SRAM Write Cycle
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time
20
15
15
8
25
20
20
10
0
45
30
30
15
0
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
WC
PWE
SCE
SD
WC
WP
CW
DW
DH
Write Pulse Width
Chip Enable To End of Write
Data Setup to End of Write
Data Hold After End of Write
Address Setup to End of Write
Address Setup to Start of Write
Address Hold After End of Write
Write Enable to Output Disable
Output Active after End of Write
Byte Enable to End of Write
0
HD
15
0
20
0
30
0
AW
AW
AS
SA
0
0
0
HA
WR
WZ
OW
8
10
15
HZWE
3
3
3
LZWE
BW
-
15
20
30
Switching Waveforms
Figure 6. SRAM Read Cycle #1: Address Controlled
W5&
$GGUHVV
$GGUHVVꢀ9DOLG
W$$
2XWSXWꢀ'DWDꢀ9DOLG
3UHYLRXVꢀ'DWDꢀ9DOLG
W2+$
'DWDꢀ2XWSXW
Notes
15. WE must be HIGH during SRAM read cycles.
16. Device is continuously selected with CE, OE and BHE / BLE LOW.
17. Measured ±200 mV from steady state output voltage.
18. If WE is LOW when CE goes LOW, the outputs remain in the high impedance state.
19. HSB must remain HIGH during READ and WRITE cycles.
Document #: 001-45754 Rev. *B
Page 9 of 24
PRELIMINARY
CY14B102L, CY14B102N
Figure 7. SRAM Read Cycle #2: CE and OE Controlled
$GGUHVV
&(
$GGUHVVꢀ9DOLG
W5&
W+=&(
W$&(
W$$
W/=&(
W+=2(
W'2(
2(
W+=%(
W/=2(
W'%(
%+(ꢍꢀ%/(
W/=%(
+LJKꢀ,PSHGDQFH
'DWDꢀ2XWSXW
2XWSXWꢀ'DWDꢀ9DOLG
W38
W3'
$FWLYH
,
6WDQGE\
&&
Figure 8. SRAM Write Cycle #1: WE Controlled
W:&
$GGUHVV
$GGUHVVꢀ9DOLG
W6&(
W+$
&(
W%:
%+(ꢍꢀ%/(
W$:
W3:(
:(
'DWDꢀ,QSXW
'DWDꢀ2XWSXW
W6$
W+'
W6'
,QSXWꢀ'DWDꢀ9DOLG
W/=:(
W+=:(
+LJKꢀ,PSHGDQFH
3UHYLRXVꢀ'DWD
Notes
20. CE or WE must be >V during address transitions.
IH
Document #: 001-45754 Rev. *B
Page 10 of 24
PRELIMINARY
CY14B102L, CY14B102N
Figure 9. SRAM Write Cycle #2: CE Controlled
W:&
$GGUHVV
&(
$GGUHVVꢀ9DOLG
W6&(
W6$
W+$
W%:
%+(ꢍꢀ%/(
:(
W$:
W3:(
W6'
W+'
'DWDꢀ,QSXW
,QSXWꢀ'DWDꢀ9DOLG
+LJKꢀ,PSHGDQFH
'DWDꢀ2XWSXW
Figure 10. SRAM Write Cycle #3: BHE and BLE Controlled
W:&
$GGUHVV
&(
$GGUHVVꢀ9DOLG
W6&(
W6$
W+$
W%:
%+(ꢍꢀ%/(
:(
W$:
W3:(
W6'
W+'
'DWDꢀ,QSXW
,QSXWꢀ'DWDꢀ9DOLG
+LJKꢀ,PSHGDQFH
'DWDꢀ2XWSXW
Document #: 001-45754 Rev. *B
Page 11 of 24
PRELIMINARY
CY14B102L, CY14B102N
AutoStore/Power Up RECALL
20 ns
25 ns
45 ns
Parameters
Description
Unit
Min
Max
20
Min
Max
20
Min
Max
20
t
t
t
Power Up RECALL Duration
STORE Cycle Duration
ms
ms
ns
V
HRECALL
8
8
8
STORE
DELAY
Time Allowed to Complete SRAM Cycle
Low Voltage Trigger Level
VCC Rise Time
20
25
25
V
t
2.65
2.65
2.65
SWITCH
150
150
150
μs
V
VCCRISE
V
HSB Output Driver Disable Voltage
HSB To Output Active Time
HSB High Active Time
1.9
5
1.9
5
1.9
5
HDIS
LZHSB
HHHD
t
t
μs
ns
500
500
500
Switching Waveforms
Figure 11. AutoStore or Power Up RECALL
96:,7&+
9+',6
1RWHꢁꢁ
1RWHꢁꢁ
99&&5,6(
W6725(
W6725(
1RWHꢁꢉ
W+++'
W+++'
+6%ꢀ287
$XWRVWRUH
W'(/$<
W/=+6%
W/=+6%
W'(/$<
32:(5ꢋ
83
5(&$//
W+5(&$//
W+5(&$//
5HDGꢀ ꢀ:ULWH
,QKLELWHG
ꢎ5:,ꢏ
5HDGꢀ ꢀ:ULWH
5HDGꢀ ꢀ:ULWH
32:(5ꢋ83
5(&$//
%52:1
287
$XWRVWRUH
32:(5
'2:1
$XWRVWRUH
32:(5ꢋ83
5(&$//
Notes
21. t
starts from the time V rises above V
SWITCH.
HRECALL
CC
22. If an SRAM write has not taken place since the last nonvolatile cycle, no AutoStore or Hardware Store takes place.
23. On a Hardware STORE, Software Store / Recall, AutoStore Enable / Disable and AutoStore initiation, SRAM operation continues to be enabled for time t
.
DELAY
24. Read and Write cycles are ignored during STORE, RECALL, and while VCC is below V
SWITCH.
25. HSB pin is driven HIGH to VCC only by internal 100kOhm resistor, HSB driver is disabled.
Document #: 001-45754 Rev. *B
Page 12 of 24
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