CY8C24223A, CY8C24423A
PSoC® Programmable System-on-Chip™
■ Additional System Resources
❐ I C™ Slave, Master, and Multi-Master to 400 kHz
❐ Watchdog and Sleep Timers
❐ User-Configurable Low Voltage Detection
❐ Integrated Supervisory Circuit
Features
2
■ Powerful Harvard Architecture Processor
❐ M8C Processor Speeds to 12 MHz
❐ 8x8 Multiply, 32-Bit Accumulate
❐ Low Power at High Speed
❐ On-Chip Precision Voltage Reference
❐ 4.75V to 5.25V Operating Voltage
❐ Extended Temperature Range: -40°C to +125°C
■ Complete Development Tools
❐ Free Development Software (PSoC Designer™)
❐ Full-Featured, In-Circuit Emulator and Programmer
❐ Full Speed Emulation
■ Advanced Peripherals (PSoC Blocks)
❐ Six Rail-to-Rail Analog PSoC Blocks Provide:
• Up to 14-Bit ADCs
❐ Complex Breakpoint Structure
• Up to 9-Bit DACs
❐ 128K Bytes Trace Memory
• Programmable Gain Amplifiers
• Programmable Filters and Comparators
❐ Four Digital PSoC Blocks Provide:
• 8 to 32-Bit Timers, Counters, and PWMs
• CRC and PRS Modules
Logic Block Diagram
Analog
Port 2 Port 1 Port 0
Drivers
PSoC CORE
• Full-Duplex UART
• Multiple SPI™ Masters or Slaves
• Connectable to all GPIO Pins
❐ Complex Peripherals by Combining Blocks
System Bus
Global Digital Interconnect
Global Analog Interconnect
■ Precision, Programmable Clocking
❐ Internal ± 4% 24 MHz Oscillator
SRAM
256 Bytes
SROM
Flash 4K
❐ High Accuracy 24 MHz with Optional 32 kHz Crystal and PLL
❐ Optional External Oscillator, up to 24 MHz
❐ Internal Oscillator for Watchdog and Sleep
Sleep and
Watchdog
CPUCore(M8C)
Interrupt
Controller
■ Flexible On-Chip Memory
Multiple Clock Sources
(IncludesIMO,ILO,PLL,andECO)
❐ 4K Bytes Flash Program Storage 100 Erase/Write Cycles
❐ 256 Bytes SRAM Data Storage
❐ In-System Serial Programming (ISSP)
❐ Partial Flash Updates
DIGITAL SYSTEM
ANALOG SYSTEM
Analog
Ref
Analog
Digital
❐ Flexible Protection Modes
Block
Array
Block Array
■ Programmable Pin Configurations
❐ 25 mA Sink on All GPIO
❐ Pull Up, Pull Down, High Z, Strong, or Open Drain Drive
Modes on All GPIO
(1 Row,
4 Blocks)
(2 Columns,
6 Blocks)
Analog
Input
Muxing
❐ Up to Ten Analog Inputs on GPIO
❐ Two 30 mA Analog Outputs on GPIO
❐ Configurable Interrupt on All GPIO
POR and LVD
System Resets
Internal
Voltage
Ref.
Digital
Clocks
Multiply
Accum .
I2C
Decimator
SYSTEM RESOURCES
Cypress Semiconductor Corporation
Document Number: 3-12029 Rev. *E
•
198 Champion Court
•
San Jose, CA 95134-1709
•
408-943-2600
Revised December 11, 2008
CY8C24223A, CY8C24423A
Figure 2. Analog System Block Diagram
Analog System
The Analog System is composed of six configurable blocks, each
comprised of an opamp circuit allowing the creation of complex
analog signal flows. Analog peripherals are very flexible and can
be customized to support specific application requirements.
Some of the more common PSoC analog functions (most
available as user modules) are:
P0[7]
P0[5]
P0[6]
P0[4]
P0[3]
P0[1]
P0[2]
P0[0]
■ Analog-to-digital converters (up to two, with 6 to 14-bit
resolution, selectable as Incremental, Delta Sigma, and SAR)
P2[6]
P2[4]
■ Filters (two and four pole band-pass, low-pass, and notch)
■ Amplifiers (up to two, with selectable gain to 48x)
■ Instrumentation amplifiers (one with selectable gain to 93x)
■ Comparators (up to two, with 16 selectable thresholds)
■ DACs (up to two, with 6 to 9-bit resolution)
P2[3]
P2[1]
P2[2]
P2[0]
■ Multiplying DACs (up to two, with 6 to 9-bit resolution)
■ High current output drivers (two with 30 mA drive as a PSoC
Core resource)
Array Input Configuration
■ 1.3V reference (as a System Resource)
■ DTMF Dialer
ACI0[1:0]
ACI1[1:0]
■ Modulators
■ Correlators
Block Array
■ Peak Detectors
ACB00
ASC10
ASD20
ACB01
■ Many other topologies possible
Analog blocks are arranged in a column of three, which includes
one CT (Continuous Time) and two SC (Switched Capacitor)
ASD11
ASC21
Analog Reference
Interface to
Digital System
Reference
Generators
Ref Hi
Ref Lo
AGND
AGNDIn
Ref In
Bandgap
M8C Interface (Address Bus, Data Bus, Etc.)
Document Number: 3-12029 Rev. *E
Page 3 of 31
CY8C24223A, CY8C24423A
Additional System Resources
Getting Started
System Resources, some of which have been previously listed,
provide additional capability useful to complete systems.
Additional resources include a multiplier, decimator, switch mode
pump, low voltage detection, and power on reset. Brief
statements describing the merits of each system resource follow:
The quickest path to understanding the PSoC silicon is by
reading this data sheet and using the PSoC Designer Integrated
Development Environment (IDE). This data sheet is an overview
of the PSoC integrated circuit and presents specific pin, register,
and electrical specifications. For in-depth information, along with
detailed programming information, refer the PSoC Program-
mable Sytem-on-Chip Technical Reference Manual.
■ Digital clock dividers provide three customizable clock
frequencies for use in applications. The clocks can be routed
to both the digital and analog systems. Additional clocks can
be generated using digital PSoC blocks as clock dividers.
For up-to-date Ordering, Packaging, and Electrical Specification
information, refer the latest PSoC device data sheets on the web
■ A multiply accumulate (MAC) provides a fast 8-bit multiplier
with 32-bit accumulate, to assist in both general math as well
as digital filters.
Development Kits
Development Kits are available from the following distributors:
Digi-Key, Avnet, Arrow, and Future. The Cypress Online Store
contains development kits, C compilers, and all accessories for
PSoC development. Go to the Cypress Online Store web site at
http://www.cypress.com, click the Online Store shopping cart
icon at the bottom of the web page, and click PSoC (Program-
mable System-on-Chip) to view a current list of available items.
■ The decimator provides a custom hardware filter for digital
signal processing applications including the creation of Delta
Sigma ADCs.
■ TheI2Cmoduleprovides100and400kHzcommunicationover
two wires. Slave, master, and multi-master modes are all
supported.
■ Low Voltage Detection (LVD) interrupts can signal the
application of falling voltage levels, while the advanced POR
(Power On Reset) circuit eliminates the need for a system
supervisor.
Technical Training
Free PSoC technical training is available for beginners and is
taught by a marketing or application engineer over the phone.
PSoC training classes cover designing, debugging, advanced
analog, and application-specific classes covering topics, such as
Design Support located on the left side of the web page, and
select Technical Training for more details.
■ An internal 1.3V reference provides an absolute reference for
the analog system, including ADCs and DACs.
PSoC Device Characteristics
Depending on your PSoC device characteristics, the digital and
analog systems can have 16, 8, or 4 digital blocks and 12, 6, or
4 analog blocks. The following table lists the resources available
for specific PSoC device groups. The PSoC device covered by
this data sheet is highlighted.
Consultants
Certified PSoC Consultants offer everything from technical
assistance to completed PSoC designs. To contact or become a
Support located on the left side of the web page, and select
CYPros Consultants.
Table 1. PSoC Device Characteristics
Technical Support
PSoC Part
Number
PSoC application engineers take pride in fast and accurate
response. They can be reached with a four-hour guaranteed
CY8C29x66
CY8C27x43
up to 4
64
16 12
4
4
4
4
12 2K
32K
16K
Application Notes
up to 2
44
8
12
12 256
Bytes
A long list of application notes can assist you in every aspect of
your design effort. To view the PSoC application notes, go to the
http://www.cypress.com web site and select Application Notes
under the Design Resources list located in the center of the web
page. Application notes are listed by date as default.
CY8C24x94
CY8C24x23
49
1
4
4
48
12
2
2
2
2
6
6
1K
16K
4K
up to 1
24
256
Bytes
CY8C24x23A up to 1
24
4
4
4
12
28
8
2
0
0
2
2
2
6
256
Bytes
4K
8K
4K
CY8C21x34
up to 1
28
4a 512
Bytes
4a 256
Bytes
CY8C21x23
16
1
a. Limited analog functionality.
Document Number: 3-12029 Rev. *E
Page 4 of 31
CY8C24223A, CY8C24423A
PSoC Designer Software Subsystems
Development Tools
PSoC Designer is a Microsoft® Windows-based, integrated
Device Editor
development
environment
for
the
Programmable
The Device Editor subsystem allows the user to select different
onboard analog and digital components called user modules
using the PSoC blocks. Examples of user modules are ADCs,
DACs, Amplifiers, and Filters.
System-on-Chip (PSoC) devices. The PSoC Designer IDE and
application runs on Windows NT 4.0, Windows 2000, Windows
PSoC Designer helps the customer to select an operating
configuration for the PSoC, write application code that uses the
PSoC, and debug the application. This system provides design
database management by project, an integrated debugger with
In-Circuit Emulator, in-system programming support, and the
CYASM macro assembler for the CPUs.
The device editor also supports easy development of multiple
configurations and dynamic reconfiguration. Dynamic
configuration allows for changing configurations at run time.
PSoC Designer sets up power on initialization tables for selected
PSoC block configurations and creates source code for an
application framework. The framework contains software to
operate the selected components and, if the project uses more
than one operating configuration, contains routines to switch
between different sets of PSoC block configurations at run time.
PSoC Designer can print out a configuration sheet for a given
project configuration for use during application programming in
conjunction with the Device Data Sheet. After the framework is
generated, the user can add application-specific code to flesh
out the framework. It is also possible to change the selected
components and regenerate the framework.
PSoC Designer also supports a high-level C language compiler
developed specifically for the devices in the family.
Figure 3. PSoC Designer Subsystems
Context
Graphical Designer
PSoC
Sensitive
Interface
Help
Designer
Design Browser
The Design Browser allows users to select and import
preconfigured designs into the user’s project. Users can easily
browse
a
catalog of preconfigured designs to facilitate
time-to-design. Examples provided in the tools include a
300-baud modem, LIN Bus master and slave, fan controller, and
magnetic card reader.
Importable
Design
Database
PSoC
Configuration
Sheet
Application Editor
Device
Database
In the Application Editor you can edit your C language and
Assembly language source code. You can also assemble,
compile, link, and build.
PSoC
Designer
Core
Application
Database
Assembler. The macro assembler allows the assembly code to
be merged seamlessly with C code. The link libraries automati-
cally use absolute addressing or can be compiled in relative
mode, and linked with other software modules to get absolute
addressing.
Manufacturing
Information
File
Engine
Project
Database
User
Modules
Library
C Language Compiler. A C language compiler is available that
supports Cypress MicroSystems’ PSoC family devices. Even if
you have never worked in the C language before, the product
quickly allows you to create complete C programs for the PSoC
family devices.
The embedded, optimizing C compiler provides all the features
of C tailored to the PSoC architecture. It comes complete with
embedded libraries providing port and bus operations, standard
keypad and display support, and extended math functionality.
Emulation
Pod
In-Circuit
Emulator
Device
Programmer
Document Number: 3-12029 Rev. *E
Page 5 of 31
CY8C24223A, CY8C24423A
Debugger
of resolution. The user module parameters permit you to
establish the pulse width and duty cycle. User modules also
provide tested software to cut your development time. The user
module application programming interface (API) provides
high-level functions to control and respond to hardware events
at run-time. The API also provides optional interrupt service
routines that you can adapt as needed.
The PSoC Designer Debugger subsystem provides hardware
in-circuit emulation, allowing the designer to test the program in
a physical system while providing an internal view of the PSoC
device. Debugger commands allow the designer to read and
program and read and write data memory, read and write IO
registers, read and write CPU registers, set and clear break-
points, and provide program run, halt, and step control. The
debugger also allows the designer to create a trace buffer of
registers and memory locations of interest.
The API functions are documented in user module data sheets
that are viewed directly in the PSoC Designer IDE. These data
sheets explain the internal operation of the user module and
provide performance specifications. Each data sheet describes
the use of each user module parameter and documents the
setting of each register controlled by the user module.
Online Help System
The online help system displays online, context-sensitive help
for the user. Designed for procedural and quick reference, each
functional subsystem has its own context-sensitive help. This
system also provides tutorials and links to FAQs and an Online
Support Forum to aid the designer in getting started.
The development process starts when you open a new project
and bring up the Device Editor, a graphical user interface (GUI)
for configuring the hardware. You pick the user modules you
need for your project and map them onto the PSoC blocks with
point-and-click simplicity. Next, you build signal chains by
interconnecting user modules to each other and the IO pins. At
this stage, you also configure the clock source connections and
enter parameter values directly or by selecting values from
drop-down menus. When you are ready to test the hardware
configuration or move on to developing code for the project, you
perform the “Generate Application” step. This causes PSoC
Designer to generate source code that automatically configures
the device to your specification and provides the high-level user
module API functions.
Hardware Tools
In-Circuit Emulator
A low cost, high functionality ICE (In-Circuit Emulator) is
available for development support. This hardware has the
capability to program single devices.
The emulator consists of a base unit that connects to the PC by
way of the parallel or USB port. The base unit is universal and
operates with all PSoC devices. Emulation pods for each device
family are available separately. The emulation pod takes the
place of the PSoC device in the target board and performs full
speed (12 MHz) operation.
Figure 4. User Module and Source Code Development Flows
Device Editor
Designing with User Modules
Placement
User
Module
Selection
Source
Code
Generator
and
Parameter
-ization
The development process for the PSoC device differs from that
of a traditional fixed function microprocessor. The configurable
analog and digital hardware blocks give the PSoC architecture a
unique flexibility that pays dividends in managing specification
change during development and by lowering inventory costs.
These configurable resources, called PSoC Blocks, have the
ability to implement a wide variety of user-selectable functions.
Each block has several registers that determine its function and
connectivity to other blocks, multiplexers, buses and to the IO
pins. Iterative development cycles permit you to adapt the
hardware as well as the software. This substantially lowers the
risk of having to select a different part to meet the final design
requirements.
Generate
Application
Application Editor
Source
Code
Editor
Project
Manager
Build
Manager
To speed the development process, the PSoC Designer
Integrated Development Environment (IDE) provides a library of
pre-built, pre-tested hardware peripheral functions, called “User
Modules.” User modules make selecting and implementing
peripheral devices simple, and come in analog, digital, and
mixed signal varieties. The standard User Module library
contains over 50 common peripherals such as ADCs, DACs
Timers, Counters, UARTs, and other not-so common peripherals
such as DTMF Generators and Bi-Quad analog filter sections.
Build
All
Debugger
Event &
Breakpoint
Manager
Each user module establishes the basic register settings that
implement the selected function. It also provides parameters that
allow you to tailor its precise configuration to your particular
application. For example, a Pulse Width Modulator User Module
configures one or more digital PSoC blocks, one for each 8 bits
Interface
to ICE
Storage
Inspector
Document Number: 3-12029 Rev. *E
Page 6 of 31
CY8C24223A, CY8C24423A
The next step is to write your main program, and any
sub-routines using PSoC Designer’s Application Editor
subsystem. The Application Editor includes a Project Manager
that allows you to open the project source code files (including
all generated code files) from a hierarchal view. The source code
editor provides syntax coloring and advanced edit features for
both C and assembly language. File search capabilities include
simple string searches and recursive “grep-style” patterns. A
single mouse click invokes the Build Manager. It employs a
professional-strength “makefile” system to automatically analyze
all file dependencies and run the compiler and assembler as
necessary. Project-level options control optimization strategies
used by the compiler and linker. Syntax errors are displayed in a
console window. Double clicking the error message takes you
directly to the offending line of source code. When all is correct,
the linker builds a HEX file image suitable for programming.
Table 2. Acronyms (continued)
Acronym
LSb
Description
least-significant bit
LVD
low voltage detect
most-significant bit
program counter
MSb
PC
PLL
phase-locked loop
power on reset
POR
PPOR
precision power on reset
®
PSoC
Programmable System-on-Chip™
pulse width modulator
PWM
SC
switched capacitor
The last step in the development process takes place inside the
PSoC Designer’s Debugger subsystem. The Debugger
downloads the HEX image to the In-Circuit Emulator (ICE) where
it runs at full speed. Debugger capabilities rival those of systems
costing many times more. In addition to traditional single-step,
run-to-breakpoint and watch-variable features, the Debugger
provides a large trace buffer and allows you define complex
breakpoint events that include monitoring address and data bus
values, memory locations and external signals.
SRAM
static random access memory
Units of Measure
A units of measure table is located in the Electrical Specifications
measure the PSoC devices.
Numeric Naming
Hexadecimal numbers are represented with all letters in
uppercase with an appended lowercase ‘h’ (for example, ‘14h’ or
‘3Ah’). Hexadecimal numbers may also be represented by a ‘0x’
prefix, the C coding convention. Binary numbers have an
appended lowercase ‘b’ (for example, 01010100b’ or
‘01000011b’). Numbers not indicated by an ‘h’ or ‘b’ are decimal.
Document Conventions
Acronyms Used
The following table lists the acronyms that are used in this
document.
Table 2. Acronyms
Acronym
AC
Description
alternating current
ADC
API
analog-to-digital converter
application programming interface
central processing unit
continuous time
CPU
CT
DAC
DC
digital-to-analog converter
direct current
ECO
external crystal oscillator
EEPROM electrically erasable programmable read-only
memory
FSR
GPIO
GUI
HBM
ICE
full scale range
general purpose IO
graphical user interface
human body model
in-circuit emulator
ILO
internal low speed oscillator
internal main oscillator
input/output
IMO
IO
IPOR
imprecise power on reset
Document Number: 3-12029 Rev. *E
Page 7 of 31
CY8C24223A, CY8C24423A
Pinouts
The CY8C24x23A automotive PSoC device is available in a variety of packages which are listed and illustrated in the following tables.
Every port pin (labeled with a “P”) is capable of Digital IO. However, Vss, Vdd, and XRES are not capable of Digital IO.
20-Pin Part Pinout
Table 3. 20-Pin Part Pinout (SSOP)
Type
Figure 5. CY8C24223A 20-Pin PSoC Device
Pin
No.
Pin
Name
Description
Digital Analog
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
Vdd
1
2
3
4
5
6
7
8
9
20
19
18
17
16
15
14
13
12
11
1
IO
IO
I
P0[7] Analog column mux input
P0[6], A,I
2
IO
P0[5] Analog column mux input and column
output
P0[4], A,I
P0[2], A,I
3
IO
IO
I
P0[3] Analog column mux input and column
output
Vss
P0[0], A,I
XRES
P1[6]
SSOP
I2CSCL,P1[7]
I2C SDA,P1[5]
P1[3]
4
5
6
7
8
9
IO
P0[1] Analog column mux input
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
Power
IO
Vss
Ground connection
I2CSCL,XTALin,P1[1]
Vss
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
P1[3]
10
IO
IO
IO
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
10 Power
11 IO
Vss
Ground connection
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
12 IO
13 IO
14 IO
15 Input
P1[2]
P1[4] Optional External Clock Input (EXTCLK)
P1[6]
XRES Active high external reset with internal pull
down
16 IO
17 IO
18 IO
19 IO
20 Power
I
I
I
I
P0[0] Analog column mux input
P0[2] Analog column mux input
P0[4] Analog column mux input
P0[6] Analog column mux input
Vdd
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 3-12029 Rev. *E
Page 8 of 31
CY8C24223A, CY8C24423A
28-Pin Part Pinout
Table 4. 28-Pin Part Pinout (SSOP)
Pi
n
Type
Figure 6. CY8C24423A 28-Pin PSoC Device
Pin
Description
Digi- Ana-
No
.
Name
tal
log
A, I,P0[7]
A,IO, P0[5]
A,IO, P0[3]
A,I, P0[1]
1
2
3
Vdd
P0[6], A,I
P0[4], A,I
28
27
26
25
24
23
22
21
20
19
18
17
16
15
1
2
IO
I
P0[7] Analog column mux input
IO
IO
IO
IO
I
P0[5] Analog column mux input and column
output
P0[2], A,I
4
P2[7]
P0[0], A,I
5
P2[5]
P2[6],ExternalVRef
P2[4],ExternalAGND
P2[2], A,I
6
7
8
3
P0[3] Analog column mux input and column
output
A,I, P2[3]
A, I,P2[1]
SSOP
4
5
6
7
8
9
IO
P0[1] Analog column mux input
Vss
9
P2[0], A,I
IO
P2[7]
I2CSCL,P1[7]
I2CSDA,P1[5]
P1[3]
XRES
P1[6]
10
11
12
13
14
IO
P2[5]
P1[4],EXTCLK
P1[2]
P1[0],XTALout,I2CSDA
IO
I
I
P2[3] Direct switched capacitor block input
P2[1] Direct switched capacitor block input
I2CSCL,XTALin,P1[1]
Vss
IO
Power
Vss
Ground connection
10 IO
11 IO
12 IO
13 IO
P1[7] I2C Serial Clock (SCL)
P1[5] I2C Serial Data (SDA)
P1[3]
P1[1] Crystal Input (XTALin), I2C Serial Clock
(SCL), ISSP-SCLK*
14 Power
15 IO
Vss
Ground connection
P1[0] Crystal Output (XTALout), I2C Serial Data
(SDA), ISSP-SDATA*
16 IO
17 IO
18 IO
19 Input
P1[2]
P1[4] Optional External Clock Input (EXTCLK)
P1[6]
XRES Active high external reset with internal pull
down
20 IO
21 IO
22 IO
23 IO
24 IO
25 IO
26 IO
27 IO
28 Power
I
I
P2[0] Direct switched capacitor block input
P2[2] Direct switched capacitor block input
P2[4] External Analog Ground (AGND)
P2[6] External Voltage Reference (VRef)
P0[0] Analog column mux input
I
I
I
I
P0[2] Analog column mux input
P0[4] Analog column mux input
P0[6] Analog column mux input
Vdd
Supply voltage
LEGEND: A = Analog, I = Input, and O = Output.
* These are the ISSP pins, which are not High Z at POR (Power On Reset).
See the PSoC Programmable System-on-Chip Technical Reference Manual for details.
Document Number: 3-12029 Rev. *E
Page 9 of 31
CY8C24223A, CY8C24423A
Register Mapping Tables
Register Reference
The PSoC device has a total register address space of 512
bytes. The register space is referred to as IO space and is
divided into two banks. The XOI bit in the Flag register (CPU_F)
determines which bank the user is currently in. When the XOI bit
is set the user is in Bank 1.
This section lists the registers of the CY8C24x23A automotive
PSoC device. For detailed register information, refer the PSoC
Programmable System-on-Chip Technical Reference Manual.
Register Conventions
Note In the following register mapping tables, blank fields are
Reserved and must not be accessed.
Abbreviations Used
The register conventions specific to this section are listed in the
following table.
Table 5. Abbreviations
Convention
Description
Read register or bit(s)
R
W
L
Write register or bit(s)
Logical register or bit(s)
Clearable register or bit(s)
Access is bit specific
C
#
Document Number: 3-12029 Rev. *E
Page 10 of 31
CY8C24223A, CY8C24423A
Table 6. Register Map Bank 0 Table: User Space
PRT0DR
PRT0IE
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
57
58
59
5A
5B
5C
5D
5E
5F
60
61
62
63
64
65
66
67
68
69
6A
6B
6C
6D
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
80
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
97
98
99
9A
9B
9C
9D
9E
9F
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
AA
AB
AC
AD
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
D7
D8
D9
DA
DB
DC
DD
DE
DF
E0
E1
E2
E3
E4
E5
E6
E7
E8
E9
EA
EB
EC
ED
PRT0GS
PRT0DM2
PRT1DR
PRT1IE
PRT1GS
PRT1DM2
PRT2DR
PRT2IE
PRT2GS
PRT2DM2
ASD20CR0
ASD20CR1
ASD20CR2
ASD20CR3
ASC21CR0
ASC21CR1
ASC21CR2
ASC21CR3
RW
RW
RW
RW
RW
RW
RW
RW
12
13
14
15
16
17
18
19
1A
1B
1C
1D
1E
1F
20
21
22
23
24
25
26
27
28
29
2A
2B
2C
2D
I2C_CFG
I2C_SCR
I2C_DR
RW
#
RW
#
I2C_MSCR
INT_CLR0
INT_CLR1
RW
RW
INT_CLR3
INT_MSK3
RW
RW
DBB00DR0
DBB00DR1
DBB00DR2
DBB00CR0
DBB01DR0
DBB01DR1
DBB01DR2
DBB01CR0
DCB02DR0
DCB02DR1
DCB02DR2
DCB02CR0
DCB03DR0
DCB03DR1
#
AMX_IN
RW
INT_MSK0
INT_MSK1
INT_VC
RW
RW
RC
W
W
RW
#
ARF_CR
CMP_CR0
ASY_CR
CMP_CR1
RW
#
RES_WDT
DEC_DH
DEC_DL
DEC_CR0
DEC_CR1
MUL_X
#
RC
RC
RW
RW
W
W
RW
#
#
RW
#
W
RW
#
MUL_Y
W
MUL_DH
MUL_DL
ACC_DR1
ACC_DR0
R
R
#
RW
RW
W
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Document Number: 3-12029 Rev. *E
Page 11 of 31
CY8C24223A, CY8C24423A
Table 6. Register Map Bank 0 Table: User Space (continued)
DCB03DR2
DCB03CR0
2E
2F
30
31
32
33
34
35
36
37
38
39
3A
3B
3C
3D
3E
3F
RW
#
6E
6F
70
71
72
73
74
75
76
77
78
79
7A
7B
7C
7D
7E
7F
AE
AF
B0
B1
B2
B3
B4
B5
B6
B7
B8
B9
BA
BB
BC
BD
BE
BF
ACC_DR3
ACC_DR2
EE
EF
F0
F1
F2
F3
F4
F5
F6
F7
F8
F9
FA
FB
FC
FD
FE
FF
RW
RW
ACB00CR3
ACB00CR0
ACB00CR1
ACB00CR2
ACB01CR3
ACB01CR0
ACB01CR1
ACB01CR2
RW
RW
RW
RW
RW
RW
RW
RW
RDI0RI
RW
RW
RW
RW
RW
RW
RW
RDI0SYN
RDI0IS
RDI0LT0
RDI0LT1
RDI0RO0
RDI0RO1
CPU_F
RL
CPU_SCR1
CPU_SCR0
#
#
Blank fields are Reserved and must not be accessed.
# Access is bit specific.
Table 7. Register Map Bank 1 Table: Configuration Space
PRT0DM0
PRT0DM1
PRT0IC0
PRT0IC1
PRT1DM0
PRT1DM1
PRT1IC0
PRT1IC1
PRT2DM0
PRT2DM1
PRT2IC0
PRT2IC1
00
01
02
03
04
05
06
07
08
09
0A
0B
0C
0D
0E
0F
10
11
12
13
14
15
16
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
RW
40
41
42
43
44
45
46
47
48
49
4A
4B
4C
4D
4E
4F
50
51
52
53
54
55
56
ASC10CR0
ASC10CR1
ASC10CR2
ASC10CR3
ASD11CR0
ASD11CR1
ASD11CR2
ASD11CR3
80
RW
RW
RW
RW
RW
RW
RW
RW
C0
C1
C2
C3
C4
C5
C6
C7
C8
C9
CA
CB
CC
CD
CE
CF
D0
D1
D2
D3
D4
D5
D6
81
82
83
84
85
86
87
88
89
8A
8B
8C
8D
8E
8F
90
91
92
93
94
95
96
ASD20CR0
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