Cypress CY62136VN User Manual

CY62136VN MoBL®  
2-Mbit (128K x 16) Static RAM  
portable applications such as cellular telephones. The device  
also has an automatic power-down feature that significantly  
reduces power consumption by 99% when addresses are not  
toggling. The device can also be put into standby mode when  
Features  
• Temperature Ranges  
— Industrial: –40°C to 85°C  
deselected (CE HIGH). The input/output pins (I/O through  
0
— Automotive-A: –40°C to 85°C  
— Automotive-E: –40°C to 125°C  
• High speed: 55 ns  
I/O ) are placed in a high-impedance state when: deselected  
15  
(CE HIGH), outputs are disabled (OE HIGH), BHE and BLE  
are disabled (BHE, BLE HIGH), or during a write operation (CE  
LOW, and WE LOW).  
• Wide voltage range: 2.7V–3.6V  
• Ultra-low active, standby power  
• Easy memory expansion with CE and OE features  
• TTL-compatible inputs and outputs  
• Automatic power-down when deselected  
• CMOS for optimum speed/power  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. If Byte Low Enable  
(BLE) is LOW, then data from I/O pins (I/O through I/O ), is  
0
7
written into the location specified on the address pins (A  
0
through A ). If Byte High Enable (BHE) is LOW, then data  
16  
from I/O pins (I/O through I/O ) is written into the location  
8
15  
specified on the address pins (A through A ).  
0
16  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing the  
Write Enable (WE) HIGH. If Byte Low Enable (BLE) is LOW,  
then data from the memory location specified by the address  
• Available in standard Pb-free 44-pin TSOP Type II,  
Pb-free and non Pb-free 48-ball FBGA packages  
Functional Description[1]  
pins will appear on I/O to I/O . If Byte High Enable (BHE) is  
0
7
LOW, then data from memory will appear on I/O to I/O . See  
the Truth Table at the back of this data sheet for a complete  
description of read and write modes.  
8
15  
The CY62136VN is a high-performance CMOS static RAM  
organized as 128K words by 16 bits. This device features  
advanced circuit design to provide ultra-low active current.  
®
This is ideal for providing More Battery Life(MoBL ) in  
PinConfigurations[3]  
Logic Block Diagram  
TSOP II (Forward)  
Top View  
DATA IN DRIVERS  
A10  
A9  
A8  
A7  
A6  
A5  
A4  
A3  
A2  
A1  
A0  
44  
1
A
A
A
A
A
CE  
I/O  
I/O  
I/O  
A
A
A
4
3
2
1
0
5
6
43  
42  
41  
40  
39  
38  
2
3
4
5
6
7
OE  
BHE  
BLE  
I/O  
I/O  
I/O  
I/O  
V
V
I/O  
I/O  
I/O  
I/O  
NC  
A
A
A
A
128K x 16  
RAM Array  
I/O0 – I/O7  
I/O8 – I/O15  
7
0
15  
37  
36  
35  
34  
33  
8
1
2
14  
13  
12  
9
10  
11  
12  
13  
I/O  
V
3
SS  
CC  
V
SS  
CC  
32  
I/O  
I/O  
I/O  
I/O  
4
5
6
7
11  
10  
31  
30  
29  
28  
14  
15  
16  
17  
18  
19  
20  
21  
22  
9
8
COLUMN DECODER  
WE  
27  
26  
25  
A
8
9
10  
11  
16  
15  
14  
BHE  
WE  
CE  
OE  
BLE  
A
A
A
24  
23  
13  
A
NC  
12  
Note:  
Cypress Semiconductor Corporation  
Document #: 001-06510 Rev. *A  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised August 3, 2006  
CY62136VN MoBL®  
Output Current into Outputs (LOW)............................ 20 mA  
Maximum Ratings  
Static Discharge Voltage...........................................> 2001V  
(per MIL-STD-883, Method 3015)  
(Above which the useful life may be impaired. For user guide-  
lines, not tested.)  
Latch-up Current.....................................................> 200 mA  
Storage Temperature ..................................65°C to +150°C  
Operating Range  
Ambient Temperature with  
Power Applied.............................................55°C to +125°C  
[5]  
Range  
Industrial  
Ambient Temperature [T ]  
V
CC  
A
Supply Voltage to Ground Potential............... –0.5V to +4.6V  
40°C to +85°C  
–40°C to +85°C  
–40°C to +125°C  
2.7V to  
3.6V  
DC Voltage Applied to Outputs  
Automotive-A  
Automotive-E  
[4]  
in High-Z State ....................................–0.5V to V + 0.5V  
CC  
[4]  
DC Input Voltage .................................–0.5V to V + 0.5V  
CC  
Electrical Characteristics Over the Operating Range  
-55  
-70  
[2]  
[2]  
Parameter  
Description  
Test Conditions  
Min. Typ.  
Max.  
Min. Typ.  
Max.  
Unit  
V
Output HIGH Voltage V = 2.7V, I = 1.0 mA  
2.4  
2.4  
V
V
V
OH  
CC  
OH  
V
V
Output LOW Voltage V = 2.7V, I = 2.1 mA  
0.4  
0.4  
OL  
IH  
CC  
OL  
Input HIGH Voltage  
V
= 3.6V  
2.2  
V
+
2.2  
V
+
CC  
CC  
CC  
0.5V  
0.5V  
V
I
Input LOW Voltage  
V
= 2.7V  
–0.5  
–1  
0.8  
+1  
+1  
–0.5  
–1  
–1  
–10  
–1  
–1  
–10  
7
0.8  
+1  
+1  
+10  
+1  
+1  
+10  
15  
15  
20  
2
V
IL  
CC  
Input Leakage  
Current  
GND < V < V  
CC  
Ind’l  
µA  
µA  
µA  
µA  
µA  
µA  
mA  
IX  
I
Auto-A  
Auto-E  
Ind’l  
–1  
I
I
Output Leakage  
Current  
GND < V < V ,  
CC  
Output Disabled  
–1  
–1  
+1  
+1  
OZ  
O
Auto-A  
Auto-E  
V
Operating  
f = f  
= 1/t  
V
= 3.6V, Ind’l  
= 0 mA,  
7
7
20  
20  
CC  
CC  
MAX  
CC  
Supply  
Current  
I
RC  
OUT  
Auto-A  
Auto-E  
Ind’l  
7
CMOS  
Levels  
7
f = 1 MHz  
1
1
2
2
1
mA  
Auto-A  
Auto-E  
Ind’l  
1
2
1
2
I
I
Automatic CE  
Power-down  
Current—  
CE > V 0.3V,  
100  
100  
100  
100  
100  
15  
15  
20  
µA  
µA  
µA  
µA  
SB1  
CC  
V
V
> V 0.3V or  
IN  
IN  
CC  
Auto-A  
Auto-E  
Ind’l  
< 0.3V, f = f  
MAX  
CMOS Inputs  
Automatic CE  
Power-down  
Current—  
CE > V 0.3V  
1
1
15  
15  
1
1
1
SB2  
CC  
V
V
> V 0.3V or  
IN  
IN  
CC  
Auto-A  
Auto-E  
< 0.3V, f = 0  
CMOS Inputs  
Capacitance[6]  
Parameter  
Description  
Input Capacitance  
Output Capacitance  
Test Conditions  
T = 25°C, f = 1 MHz,  
Max.  
Unit  
C
C
6
8
pF  
pF  
IN  
A
V
= V  
CC  
CC(typ)  
OUT  
Notes:  
4. V (min) = –2.0V for pulse durations less than 20 ns.  
IL  
5. T is the “Instant-On” case temperature.  
A
6. Tested initially and after any design or process changes that may affect these parameters.  
Document #: 001-06510 Rev. *A  
Page 3 of 12  
CY62136VN MoBL®  
Thermal Resistance[6]  
Parameter  
Description  
Test Conditions  
TSOPII  
FBGA  
Unit  
Θ
Θ
Thermal Resistance  
(Junction to Ambient)  
Still Air, soldered on a 4.25 x 1.125 inch,  
4-layer printed circuit board  
60  
55  
°C/W  
JA  
Thermal Resistance  
(Junction to Case)  
22  
16  
°C/W  
JC  
AC Test Loads and Waveforms  
R1  
R1  
ALL INPUT PULSES  
90%  
VCC  
VCC  
VCC Typ  
GND  
90%  
10%  
OUTPUT  
OUTPUT  
10%  
R2  
R2  
30 pF  
5 pF  
Rise Time:  
1 V/ns  
Fall Time:  
1 V/ns  
INCLUDING  
JIG AND  
SCOPE  
(a)  
INCLUDING  
JIG AND  
SCOPE  
(c)  
Equivalent to: THÉVENIN EQUIVALENT  
(b)  
RTH  
OUTPUT  
V
Parameters  
Value  
1105  
1550  
645  
Unit  
Ohms  
Ohms  
Ohms  
Volts  
R1  
R2  
R
V
TH  
TH  
1.75  
Data Retention Characteristics (Over the Operating Range)  
[9]  
[2]  
Parameter  
Description  
Conditions  
Min.  
Typ.  
Max. Unit  
V
V
for Data Retention  
1.0  
V
DR  
CC  
I
Data Retention Current  
V
V
= 1.0V, CE > V 0.3V,  
0.5  
7.5  
µA  
CCDR  
CC  
CC  
> V 0.3V or V < 0.3V,  
IN  
CC  
IN  
[6]  
t
t
Chip Deselect to Data  
Retention Time  
0
ns  
ns  
CDR  
[7]  
R
Operation Recovery Time  
70  
Data Retention Waveform  
DATA RETENTION MODE  
V
V
CC(min.)  
CC(min.)  
V
DR  
> 1.0 V  
V
CC  
t
t
R
CDR  
CE  
Note:  
7. Full device operation requires linear V ramp from V to VCC(min) >100 ms or stable at VCC(min) >100 ms.  
CC  
DR  
8. No input may exceed V + 0.3V  
CC  
Document #: 001-06510 Rev. *A  
Page 4 of 12  
CY62136VN MoBL®  
[9]  
Switching Characteristics Over the Operating Range  
55 ns  
70 ns  
Parameter  
Read Cycle  
Description  
Min.  
55  
Max.  
Min.  
70  
Max.  
Unit  
t
t
t
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
55  
70  
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
10  
10  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
55  
25  
70  
35  
OE LOW to Data Valid  
[10]  
OE LOW to Low-Z  
5
10  
0
5
10  
0
[10, 11]  
OE HIGH to High-Z  
25  
25  
25  
25  
[10]  
CE LOW to Low-Z  
[10, 11]  
CE HIGH to High-Z  
CE LOW to Power-up  
CE HIGH to Power-down  
BLE / BHE LOW to Data Valid  
55  
25  
70  
35  
PD  
DBE  
LZBE  
HZBE  
[10, 11]  
BLE / BHE LOW to Low-Z  
5
5
[12]  
BLE / BHE HIGH to High-Z  
25  
25  
[12, 13]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
55  
45  
45  
0
70  
60  
60  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-up to Write End  
Address Hold from Write End  
Address Set-up to Write Start  
WE Pulse Width  
HA  
0
0
SA  
40  
50  
25  
0
50  
60  
30  
0
PWE  
BW  
BLE / BHE LOW to Write End  
Data Set-up to Write End  
Data Hold from Write End  
SD  
HD  
[10, 11]  
WE LOW to High-Z  
20  
25  
HZWE  
LZWE  
[10]  
WE HIGH to Low-Z  
5
10  
Notes:  
9. Test conditions assume signal transition time of 5 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to V typ., and output loading of the specified  
CC  
I
/I and 30-pF load capacitance.  
OL OH  
10. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
11. t  
, t  
, and t  
are specified with C = 5 pF as in (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
HZOE HZCE  
HZWE  
L
12. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. Both signals must be LOW to initiate a write and either signal can  
terminate a write by going HIGH. The data input set-up and hold timing should be referenced to the rising edge of the signal that terminates the write.  
13. The minimum write cycle time for write cycle 3 (WE controlled, OE LOW) is the sum of t  
and t  
.
SD  
HZWE  
Document #: 001-06510 Rev. *A  
Page 5 of 12  
CY62136VN MoBL®  
Switching Waveforms  
[14, 15]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
[15, 16]  
DATA VALID  
Read Cycle No. 2  
t
RC  
CE  
OE  
t
PD  
HZCE  
t
t
ACE  
t
HZOE  
t
DOE  
BHE/BLE  
t
LZOE  
t
HZBE  
t
DBE  
t
LZBE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PU  
V
I
CC  
CC  
SUPPLY  
CURRENT  
50%  
50%  
I
SB  
Notes:  
14. Device is continuously selected. OE, CE = V .  
IL  
15. WE is HIGH for read cycle.  
16. Address valid prior to or coincident with CE transition LOW.  
Document #: 001-06510 Rev. *A  
Page 6 of 12  
CY62136VN MoBL®  
Switching Waveforms (continued)  
[12, 17, 18]  
Write Cycle No. 1 (WE Controlled)  
t
WC  
ADDRESS  
CE  
t
t
AW  
HA  
t
SA  
t
PWE  
WE  
t
BW  
BHE/BLE  
OE  
t
SD  
t
HD  
DATA VALID  
DATA I/O  
NOTE19  
IN  
t
HZOE  
[12, 17, 18]  
Write Cycle No. 2 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
t
HA  
AW  
t
BW  
BHE/BLE  
WE  
t
PWE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
IN  
Notes:  
17. Data I/O is high impedance if OE = V  
.
IH  
18. If CE goes HIGH simultaneously with WE HIGH, the output remains in a high-impedance state.  
19. During this period, the I/Os are in output state and input signals should not be applied.  
Document #: 001-06510 Rev. *A  
Page 7 of 12  
CY62136VN MoBL®  
Switching Waveforms (continued)  
Write Cycle No. 3 (WE Controlled, OE LOW)  
[13, 18]  
t
WC  
ADDRESS  
CE  
t
t
HA  
AW  
t
BW  
BHE/BLE  
t
SA  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
NOTE 19  
IN  
t
t
LZWE  
HZWE  
[19]  
Write Cycle No. 4 (BHE/BLE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
t
HA  
AW  
t
BW  
BHE/BLE  
t
SA  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
IN  
NOTE 19  
t
t
LZWE  
HZWE  
Document #: 001-06510 Rev. *A  
Page 8 of 12  
CY62136VN MoBL®  
Typical DC and AC Characteristics  
Normalized Operating Current  
vs. Supply Voltage  
Standby Current vs. Supply Voltage  
35  
1.4  
1.2  
MoBL  
30  
MoBL  
25  
20  
15  
1.0  
0.8  
0.6  
10  
0.4  
5
0
0.2  
0.0  
2.7  
1.0  
3.7  
2.8  
1.9  
1.7  
2.2  
2.7  
3.2  
3.7  
SUPPLY VOLTAGE (V)  
SUPPLY VOLTAGE (V)  
Access Time vs. Supply Voltage  
80  
70  
MoBL  
60  
50  
40  
30  
20  
10  
1.0  
3.7  
2.8  
1.9  
2.7  
SUPPLY VOLTAGE (V)  
Truth Table  
CE  
WE  
OE  
BHE  
BLE  
Inputs/Outputs  
High-Z  
Data Out (I/O –I/O  
Mode  
Power  
Standby (I  
H
X
X
L
L
X
L
X
Deselect/Power-down  
)
SB  
L
L
H
H
L
L
)
Read  
Read  
Active (I  
Active (I  
)
)
0
15  
CC  
CC  
H
Data Out (I/O –I/O );  
0
7
I/O –I/O in High-Z  
8
15  
L
H
L
L
H
Data Out (I/O –I/O );  
Read  
Active (I  
)
8
15  
CC  
I/O –I/O in High-Z  
0
7
L
L
L
L
L
L
H
H
H
H
L
L
H
H
H
X
X
H
L
H
L
L
H
L
L
High-Z  
Deselect/Output Disabled  
Deselect/Output Disabled  
Deselect/Output Disabled  
Deselect/Output Disabled  
Write  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
Active (I  
)
)
)
)
)
)
CC  
CC  
CC  
CC  
CC  
CC  
High-Z  
High-Z  
High-Z  
H
L
L
Data In (I/O –I/O  
)
0
15  
L
H
Data In (I/O –I/O );  
Write  
0
7
I/O –I/O in High-Z  
8
15  
L
L
X
L
H
Data In (I/O –I/O );  
Write  
Active (I  
)
8
15  
CC  
I/O –I/O in High-Z  
0
7
Document #: 001-06510 Rev. *A  
Page 9 of 12  
CY62136VN MoBL®  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
Package Type  
55  
CY62136VNLL-55ZXI  
CY62136VNLL-55BAI  
CY62136VNLL-55ZSXA  
CY62136VNLL-70ZXI  
CY62136VNLL-70BAI  
CY62136VNLL-70BAXA  
CY62136VNLL-70ZSXA  
CY62136VNLL-70ZSXE  
51-85087 44-pin TSOP II (Pb-Free)  
Industrial  
51-85096 48-Ball (7.00 mm x 7.00 mm) FBGA  
51-85087 44-pin TSOP II (Pb-Free)  
Automotive-A  
Industrial  
70  
51-85087 44-pin TSOP II (Pb-Free)  
51-85096 48-Ball (7.00 mm x 7.00 mm) FBGA  
51-85096 48-Ball (7.00 mm x 7.00 mm) FBGA (Pb-Free)  
51-85087 44-pin TSOP II (Pb-Free)  
Automotive-A  
Automotive-E  
51-85087 44-pin TSOP II (Pb-Free)  
Please contact your local Cypress sales representative for availability of these parts  
Package Diagrams  
44-pin TSOP II (51-85087)  
51-85087-*A  
Document #: 001-06510 Rev. *A  
Page 10 of 12  
CY62136VN MoBL®  
Package Diagrams (continued)  
48-Ball (7.00 mm x 7.00 mm) FBGA (51-85096)  
BOTTOM VIEW  
PIN 1 CORNER  
TOP VIEW  
Ø0.05 M C  
PIN 1 CORNER  
(LASER MARK)  
Ø0.25 M C A B  
Ø0.30 0.05(48X)  
1
2
3
4
5
6
6
5
4
3
2
1
A
B
A
B
C
D
C
D
E
F
E
F
G
H
G
H
A
A
1.875  
0.75  
3.75  
B
7.00 0.10  
7.00 0.10  
B
0.15(4X)  
51-85096-*F  
SEATING PLANE  
C
1.20 MAX.  
MoBL is a registered trademark, and More Battery Life is a trademark, of Cypress Semiconductor Corporation. All product and  
company names mentioned in this document are the products of their respective holders.  
Document #: 001-06510 Rev. *A  
Page 11 of 12  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY62136VN MoBL®  
Document History Page  
®
Document Title: CY62136VN MoBL 2-Mbit (128K x 16) Static RAM  
Document Number: 001-06510  
Orig. of  
REV.  
**  
ECN NO.  
426503  
488954  
Issue Date Change  
Description of Change  
See ECN  
See ECN  
RXU  
NXR  
New Data Sheet  
*A  
Added Automotive product  
Updated ordering Information table  
Document #: 001-06510 Rev. *A  
Page 12 of 12  

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