Cypress CY7C1007BN User Manual

CY7C107BN  
CY7C1007BN  
1M x 1 Static RAM  
Features  
Functional Description  
The CY7C107BN and CY7C1007BN are high-performance  
CMOS static RAMs organized as 1,048,576 words by 1 bit.  
Easy memory expansion is provided by an active LOW Chip  
Enable (CE) and three-state drivers. These devices have an  
automatic power-down feature that reduces power  
consumption by more than 65% when deselected.  
• High speed  
— t = 15 ns  
AA  
• CMOS for optimum speed/power  
• Automatic power-down when deselected  
• TTL-compatible inputs and outputs  
Writing to the devices is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the input pin  
(D ) is written into the memory location specified on the  
IN  
address pins (A through A ).  
0
19  
Reading from the devices is accomplished by taking Chip  
Enable (CE) LOW while Write Enable (WE) remains HIGH.  
Under these conditions, the contents of the memory location  
specified by the address pins will appear on the data output  
(D  
) pin.  
OUT  
The output pin (D  
) is placed in a high-impedance state  
OUT  
when the device is deselected (CE HIGH) or during a write  
operation (CE and WE LOW).  
The CY7C107BN is available in a standard 400-mil-wide SOJ;  
the CY7C1007BN is available in a standard 300-mil-wide SOJ  
Logic Block Diagram  
Pin Configuration  
SOJ  
Top View  
D
IN  
28  
27  
26  
1
2
3
4
5
6
A
11  
V
CC  
10  
A
A
9
A
13  
A
12  
8
A
25  
24  
A
7
INPUT BUFFER  
A0  
A1  
A2  
A3  
A
14  
A
6
23  
22  
A
15  
A
5
7
8
9
10  
11  
12  
13  
NC  
A
4
21  
20  
19  
18  
17  
A
17  
NC  
16  
A
A
3
A4  
A5  
A6  
A7  
A8  
A
19  
A
18  
2
512 x 2048  
ARRAY  
A
A
1
D
OUT  
A
D
0
OUT  
WE  
GND  
16  
15  
D
IN  
14  
CE  
POWER  
DOWN  
COLUMN  
CE  
DECODER  
WE  
Selection Guide  
7C107BN-15  
7C1007BN-15  
Maximum Access Time (ns)  
15  
80  
2
Maximum Operating Current (mA)  
Maximum CMOS Standby Current I  
(mA)  
SB2  
Cypress Semiconductor Corporation  
Document #: 001-06426 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 1, 2006  
CY7C107BN  
CY7C1007BN  
AC Test Loads and Waveforms  
R1 480Ω  
R1 480Ω  
5V  
5V  
OUTPUT  
ALL INPUT PULSES  
3.0V  
GND  
OUTPUT  
90%  
10%  
90%  
10%  
ns  
R2  
255Ω  
R2  
255Ω  
30 pF  
5 pF  
3 ns  
3  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(a)  
(b)  
Equivalentto:  
THÉVENIN EQUIVALENT  
167Ω  
OUTPUT  
1.73V  
Switching Characteristics[5] Over the Operating Range  
7C107BN-15  
7C1007BN-15  
Parameter  
Description  
Min.  
Max.  
Unit  
READ CYCLE  
t
t
t
t
t
t
t
t
Read Cycle Time  
15  
3
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
15  
15  
7
AA  
Data Hold from Address Change  
CE LOW to Data Valid  
OHA  
ACE  
LZCE  
HZCE  
PU  
[6]  
CE LOW to Low Z  
3
[6, 7]  
CE HIGH to High Z  
CE LOW to Power-Up  
0
CE HIGH to Power-Down  
15  
PD  
[8]  
WRITE CYCLE  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
15  
12  
12  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE LOW to Write End  
SCE  
AW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
WE Pulse Width  
HA  
0
SA  
12  
8
PWE  
SD  
Data Set-Up to Write End  
Data Hold from Write End  
0
HD  
[6]  
WE HIGH to Low Z  
3
LZWE  
HZWE  
[6, 7]  
WE LOW to High Z  
7
Notes:  
5. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
/I and 30-pF load capacitance.  
I
OL OH  
6. At any given temperature and voltage condition, t  
is less than t  
and t  
is less than t  
for any given device.  
HZCE  
LZCE  
HZWE  
LZWE  
7. t  
and t  
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
HZCE  
HZWE  
8. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any  
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
Document #: 001-06426 Rev. **  
Page 3 of 7  
CY7C107BN  
CY7C1007BN  
Switching Waveforms  
[10, 11]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
PREVIOUS DATA VALID  
DATA VALID  
DATA OUT  
[11, 12]  
Read Cycle No. 2  
ADDRESS  
CE  
t
RC  
t
ACE  
t
t
HZCE  
LZCE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
PD  
t
PU  
V
CC  
ICC  
ISB  
SUPPLY  
CURRENT  
50%  
50%  
[13]  
Write Cycle No. 1 (CE Controlled)  
t
WC  
ADDRESS  
t
SA  
t
SCE  
CE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
HIGH IMPEDANCE  
DATA OUT  
Notes:  
9. No input may exceed V + 0.5V.  
CC  
10. Device is continuously selected, CE = V .  
IL  
11. WE is HIGH for read cycle.  
12. Address valid prior to or coincident with CE transition LOW.  
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
Document #: 001-06426 Rev. **  
Page 4 of 7  
CY7C107BN  
CY7C1007BN  
Switching Waveforms (continued)  
[13]  
Write Cycle No. 2 (WE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
DATA IN  
DATA VALID  
t
t
LZWE  
HZWE  
HIGH IMPEDANCE  
DATA OUT  
DATA UNDEFINED  
Truth Table  
CE  
H
WE  
D
Mode  
Power  
OUT  
X
H
L
High Z  
Power-Down  
Read  
Standby (I  
)
SB  
L
Data Out  
High Z  
Active (I )  
CC  
L
Write  
Active (I )  
CC  
Ordering Information  
Speed  
Package  
Operating  
Range  
(ns)  
Ordering Code  
CY7C107BN-15VC  
CY7C1007BN-15VC  
CY7C1007BN-15VXC  
CY7C107BN-15VI  
Diagram  
51-85032  
51-85031  
51-85031  
51-85032  
Package Type  
15  
28-Lead (400-Mil) Molded SOJ  
28-Lead (300-Mil) Molded SOJ  
Commercial  
28-Lead (300-Mil) Molded SOJ (Pb-free)  
28-Lead (400-Mil) Molded SOJ  
Industrial  
Please contact local sales representative regarding availability of these parts  
Document #: 001-06426 Rev. **  
Page 5 of 7  
CY7C107BN  
CY7C1007BN  
Package Diagrams  
28-Lead (400-Mil) Molded SOJ (51-85032)  
PIN 1 I.D  
14  
1
MIN.  
MAX.  
DIMENSIONS IN INCHES  
.435  
.445  
.395  
.405  
15  
28  
.720  
.730  
SEATING PLANE  
.128  
.148  
.007  
.013  
0.004  
.026  
.032  
.360  
.380  
.050  
TYP.  
.015  
.020  
.025 MIN.  
51-85032.*B  
28-Lead (300-Mil) Molded SOJ (51-85031)  
NOTE :  
1. JEDEC STD REF MO088  
2. BODY LENGTH DIMENSION DOES NOT INCLUDE MOLD PROTRUSION/END FLASH  
MOLD PROTRUSION/END FLASH SHALL NOT EXCEED 0.006 in (0.152 mm) PER SIDE  
MIN.  
3. DIMENSIONS IN INCHES  
MAX.  
DETAIL  
A
PIN 1 ID  
EXTERNAL LEAD DESIGN  
14  
1
0.291  
0.300  
0.330  
0.350  
0.026  
0.032  
0.013  
0.019  
15  
28  
0.014  
0.020  
OPTION 1  
OPTION 2  
0.697  
0.713  
SEATING PLANE  
0.120  
0.140  
0.007  
0.013  
0.004  
A
0.262  
0.272  
0.050  
TYP.  
51-85031-*C  
0.025 MIN.  
All product or company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 001-06426 Rev. **  
Page 6 of 7  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implies that the manufacturer assumes all risk of such use and in doing so indemnifies Cypress against all charges.  
CY7C107BN  
CY7C1007BN  
Document History Page  
Document Title: CY7C107BN/CY7C1007BN 1M x 1 Static RAM  
Document Number: 001-06426  
Issue  
Date  
Orig. of  
Change  
REV.  
ECN NO.  
Description of Change  
**  
423847  
See ECN  
NXR  
New Data Sheet  
Document #: 001-06426 Rev. **  
Page 7 of 7  

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