Cypress Computer Hardware CY2048WAF User Manual

CY2048WAF  
Flash Programmable Capacitor Tuning Array Die  
for Crystal Oscillator(XO)  
Features  
Benefits  
• Flash-programmable capacitor tuning array for low  
ppm initial frequency clock output  
• Enables fine-tuning of output clock frequency by  
adjusting C of the crystal  
Load  
• Low clock output jitter  
• Allows multiple programming opportunities to correct  
errors, and control excess inventory  
— 4 ps typ. RMS period jitter  
• Enables programming of output frequency after  
packaging  
— ±30 ps typ. peak-to-peak period jitter  
• Flash-programmable dividers  
• Two-pin programming interface  
• On-chip oscillator runs from 10–48-MHz crystal  
• PPM clock output error can be adjusted in package  
• Provides flexibility in output configurations and testing  
• Enables low-power operation or output enable function  
• Five selectable post-divide options, using reference  
oscillator output  
• Provides flexibility for system applications through  
selectable instantaneous or synchronous change in  
outputs  
• Programmable asynchronous or synchronous OE and  
PWR_DWN modes  
Enables encapsulation in small-size, surface-mount  
packages  
• 2.7V to 3.6V operation  
• Controlled rise and fall times and output slew rate  
Block Diagram  
PD#/OE  
(SDATA/VPP)  
CONFIGURATION  
XIN  
CRYSTAL  
XOUT  
OSCILLATOR  
OUT  
(SCL)  
/ 1, 2, 4, 8, 16  
VSS  
VDD  
Die Pad Description  
H orizontal Scribe  
Notes:  
1
6
V D D  
O U T  
X(max): 980 µm, Y(max): 988 µm  
Scribe: X = 70 µm, Y = 86 µm  
Y (m ax)  
2
X O U T  
V ertical  
S cribe  
Bond pad opening: 85 µm x 85 µm  
Pad pitch: 175 µm (min.)  
3
4
X IN  
7C80330A  
Wafer thickness: 11 mils (Typ.)  
P D #/O E  
die#/rev  
5
V S S  
X(m ax)  
Cypress Semiconductor Corporation  
Document #: 38-07738 Rev. *A  
3901 North First Street  
San Jose, CA 95134  
408-943-2600  
Revised December 12, 2005  
 
CY2048WAF  
Output Short Circuit Current..................................... ± 50 mA  
Storage Temperature (Non-condensing) .... –55°C to +125°C  
Junction Temperature................................ –40°C to +125°C  
Data Retention @ Tj = 125°C................................> 10 years  
ESD (Human Body Model) MIL-STD-883.................> 2000V  
Absolute Maximum Conditions  
(Above which the useful life may be impaired.  
For user guidelines, not tested.)  
Supply Voltage (V )........................................–0.5 to +7.0V  
DD  
DC Input Voltage...................................... –0.5V to V + 0.5  
DD  
Crystal Specifications[1]  
Parameter  
Description  
Nominal crystal frequency  
Comments  
Fundamental mode, AT cut  
Fundamental mode  
Min. Typ. Max. Unit  
F
10  
48  
40  
MHz  
NOM  
R
Equivalent series resistance (ESR)  
1
R /R  
Ratio of third overtone mode ESR to  
fundamental mode ESR  
Ratio used because typical R values are  
much less than the maximum spec  
4.5  
3
1
1
C
C
Crystal shunt capacitance  
2
5
pF  
fF  
0
Crystal motional capacitance  
1
Operating Conditions  
Parameter  
Description  
Min.  
2.7  
–40  
Typ.  
Max.  
3.6  
125  
Unit  
V
V
Operating Voltage  
DD  
T
Junction Temperature  
°C  
pF  
pF  
pF  
pF  
pF  
ms  
J
C
C
C
Capacitance XIN, all tuning caps OFF  
Capacitance XOUT, all tuning caps OFF  
All tuning Caps OFF  
10  
10  
5
XIN  
XOUT  
L
4
6
All tuning Caps ON  
9.2  
10  
11.4  
15  
C
Output Load Capacitance  
OUT  
t
Power-up time for V to reach minimum specified  
0.05  
500  
RAMP  
DD  
voltage (power ramps must be monotonic)  
T
Start up time, 90% V to valid frequency on output  
10  
ms  
S
DD  
DC Electrical Specifications TJ = –40 to 125°C over the operating range  
Parameter  
Description  
Input Low Voltage  
Condition  
CMOS Levels  
CMOS Levels  
Min.  
Typ.  
Max.  
Unit  
V
20  
%VDD  
%VDD  
V
IL  
V
V
V
I
Input High Voltage  
80  
IH  
Output Low Voltage  
Output High Voltage  
Input Low Current  
V
V
= 2.7V–3.6V, I = 8 mA  
0.4  
OL  
OH  
DD  
DD  
OL  
= 2.7V–3.6V, I = 8 mA  
V
–0.4  
V
OL  
DD  
Input = V  
Input = V  
1
10  
10  
10  
50  
20  
25  
6
µA  
IL  
SS  
DD  
I
I
I
I
I
Input High Current  
1
µA  
IH  
Output Leakage Current  
Output Leakage Current  
Power Supply Current  
Power Down Current  
Input Pull-up resistor  
Output = V  
Output = V  
1
µA  
OZL  
OZH  
DD  
SS  
DD  
µA  
No Load, V = 3.3V, 48 MHz  
mA  
µA  
DD  
PD# = 0V  
PD  
R
V
= V  
SS  
1
3
MΩ  
kΩ  
UP  
IN  
V > = 0.8V  
80  
500  
120  
900  
150  
1500  
7
IN  
DD  
R
C
R
Output Pull-down resistor  
Input Pin Capacitance  
Crystal Feedback R  
V
= 0.5V  
DD  
kΩ  
DN  
IN  
F
IN  
PD#/OE pin  
XIN = 0  
pF  
300  
800  
kΩ  
Note:  
1. Not 100% tested.  
Document #: 38-07738 Rev. *A  
Page 3 of 7  
 
CY2048WAF  
AC Electrical Specifications[1] over the operating range, except as noted  
[1]  
Parameter  
Description  
Output Frequency  
Condition  
Min.  
0.625  
45  
Typ. Max. Unit  
F
48  
55  
MHz  
%
OUT  
DC  
Output Duty Cycle  
Rise Time  
XTAL Buffered or Divided  
Output Clock Rise Time, Measured from 20% to  
80% of V , C = 15 pF.  
50  
T
2.5  
ns  
R
DD  
OUT  
T
Fall Time  
Output Clock Fall Time, Measured from 80% to  
20% of V , C = 15 pF.  
2.5  
ns  
F
DD  
OUT  
t
t
RMS Period Jitter  
XIN = 10–48 MHz. Measured at V /2  
4
30  
15  
80  
ps  
ps  
PJ1  
DD  
[2]  
Peak-to-peak Period Jitter  
Crystal drive level  
XIN = 10–48 MHz. Measured at V /2  
PJ2  
DD  
DL  
48-MHz crystal, C = 7 pF, C = 2 pF,  
350–400  
µW  
L
0
R1 = 10 Ohms, Temp. = 25°C, V = 3.6V  
DD  
–R  
Negative Resistance  
Measured at 48 MHz, C = 10 pF, C = 5 pF  
–150  
2
L
0
F
Output Frequency Drift  
3.0V ± 10%, 3.3V ± 10% for Temp. = 25°C  
–2  
ppm  
DRIFT  
Phase Noise, Temp = 25°C, VDD = 3.3V,  
FNOM = 10MHz, XCAP = 7F (Hex)  
Offset  
10 Hz  
dBc/Hz (Typ)  
–90  
100 Hz  
1 kHz  
–115  
–130  
10 kHz  
100 kHz  
1 MHz  
–140  
–140  
–140  
Crystal Oscillator Tuning Capacitor Values  
Capacitor Bit  
Capacitance (pF) per Side  
C
C
C
C
C
C
C
C
5.000  
2.500  
1.250  
0.625  
0.313  
0.156  
0.078  
0.039  
7
6
5
4
3
2
1
0
XIN  
XOUT  
CXOUT  
CXIN  
C7  
C6  
C5 C4  
C3 C2  
C1  
C0  
C0 C1  
C2 C3  
C4  
C5 C6  
C7  
Figure 1. Programmable Load Capacitance  
Notes:  
2. T  
measured using DTS-2075, # of events set to 10, 000.  
PJ2  
Document #: 38-07738 Rev. *A  
Page 4 of 7  
 
CY2048WAF  
Timing Parameters over the operating range  
Parameter  
Description  
Min.  
Max.  
1.5T + 350  
350  
Unit  
ns  
T
T
T
Time from falling edge on PD# to stopped output, synchronous mode, T=1/F  
Time from falling edge on PD# to stopped output, asynchronous mode  
STP,SYNC  
STP,ASYNC  
PU,SYNC  
out  
ns  
Time from rising edge on PD# to output at valid frequency, synchronous mode,  
T = 1/F  
3
ms  
out  
T
T
T
T
Time from rising edge on PD# to output at valid frequency, asynchronous mode  
3
ms  
ns  
ns  
ns  
PU,ASYNC  
PZX,SYNC  
PZX,ASYNC  
PXZ,SYNC  
Time from rising edge on OE to running output, synchronous mode, T=1/F  
Time from rising edge on OE to running output, asynchronous mode  
1.5T + 350  
350  
out  
Time from falling edge on OE to high impedance output, synchronous mode,  
T = 1/F  
1.5T + 350  
out  
T
Time from falling edge on OE to high impedance output, asynchronous mode  
350  
ns  
PXZ,ASYNC  
PD  
TPU  
CLOCK  
SYNC  
Weakly pulled LOW  
Weakly pulled LOW  
TSTP  
CLOCK  
ASYNC  
T
TSTP  
Figure 2. Power-down Timing  
OE  
CLOCK  
Weakly pulled LOW  
SYNC  
TPZX  
TPXZ  
Weakly pulled LOW  
CLOCK  
ASYNC  
T
T
PXZ  
TPZX  
Figure 3. Output Enable Timing  
TS  
VDD - 10%  
0V  
POWER  
OUT  
tRAMP  
Figure 4. VDD Power-up Timing  
Document #: 38-07738 Rev. *A  
Page 5 of 7  
 
CY2048WAF  
Test and Measurement Set-up  
VDD  
Output  
CLOAD  
0.1 µF  
DUT  
GND  
Voltage and Timing Definitions  
t1  
t2  
VDD  
50% of VDD  
0V  
Clock  
Output  
Figure 5. Duty Cycle Definition  
tF  
tR  
V DD  
80% of VDD  
20% of VDD  
0V  
Clock  
Output  
Figure 6.  
Ordering Information  
Ordering Code  
Package Type  
Operating Range (TJ)  
Industrial,–40 °C to 125°C  
[3]  
CY2048WAF  
Wafer  
Note:  
3. The product is offered as tested die-on-wafer form. Contact Cypress Sales for additional programming information and support.  
All product or company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 38-07738 Rev. *A  
Page 6 of 7  
© Cypress Semiconductor Corporation, 2005. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.  
CY2048WAF  
Document History Page  
Document Title: CY2048WAF Flash Programmable Capacitor Tuning Array Die  
for Crystal Oscillator(XO)  
Document Number: 38-07738  
Orig. of  
REV. ECN NO. Issue Date Change  
Description of Change  
**  
319840 See ECN  
413511 See ECN  
RGL  
RGL  
New data sheet  
*A  
Minor Change: Pls. post in the web  
Document #: 38-07738 Rev. *A  
Page 7 of 7  
 

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