Cypress Computer Hardware CY7C1019BN User Manual

CY7C1019BN  
128K x 8 Static RAM  
Features  
Functional Description  
• High speed  
The CY7C1019BN is a high-performance CMOS static RAM  
organized as 131,072 words by 8 bits. Easy memory  
expansion is provided by an active LOW Chip Enable (CE), an  
active LOW Output Enable (OE), and three-state drivers. This  
device has an automatic power-down feature that significantly  
reduces power consumption when deselected.  
— t = 12, 15 ns  
AA  
• CMOS for optimum speed/power  
• Center power/ground pinout  
• Automatic power-down when deselected  
• Easy memory expansion with CE and OE options  
• Functionally equivalent to CY7C1019  
Writing to the device is accomplished by taking Chip Enable  
(CE) and Write Enable (WE) inputs LOW. Data on the eight I/O  
pins (I/O through I/O ) is then written into the location  
0
7
specified on the address pins (A through A ).  
0
16  
Reading from the device is accomplished by taking Chip  
Enable (CE) and Output Enable (OE) LOW while forcing Write  
Enable (WE) HIGH. Under these conditions, the contents of  
the memory location specified by the address pins will appear  
on the I/O pins.  
The eight input/output pins (I/O through I/O ) are placed in a  
0
7
high-impedance state when the device is deselected (CE  
HIGH), the outputs are disabled (OE HIGH), or during a write  
operation (CE LOW, and WE LOW).  
The CY7C1019BN is available in standard 32-pin TSOP Type  
II and 400-mil-wide SOJ packages.  
Logic Block Diagram  
Pin Configurations  
/ TSOPII  
SOJ  
Top View  
A
A
1
A
A
32  
1
0
16  
31  
30  
2
3
4
5
6
15  
A
A
14  
A
13  
2
A
29  
28  
3
I/O0  
INPUT BUFFER  
CE  
OE  
I/O  
I/O  
27  
26  
I/O  
I/O1  
I/O2  
0
1
7
A
0
I/O  
V
7
8
9
10  
11  
12  
13  
6
A
1
25  
24  
23  
22  
21  
A
2
V
CC  
SS  
A
V
3
V
CC  
I/O  
SS  
A
I/O3  
I/O4  
I/O5  
I/O6  
4
512 x 256 x 8  
ARRAY  
I/O  
I/O  
2
3
5
4
A
5
A
I/O  
A
6
A
7
WE  
A
4
12  
A
8
A
11  
20  
19  
A
5
A
10  
14  
15  
16  
A
6
A
9
A
8
18  
17  
POWER  
DOWN  
COLUMN  
DECODER  
A
7
CE  
I/O7  
WE  
OE  
Cypress Semiconductor Corporation  
Document #: 001-06425 Rev. **  
198 Champion Court  
San Jose, CA 95134-1709  
408-943-2600  
Revised February 1, 2006  
 
CY7C1019BN  
AC Test Loads and Waveforms  
R1 480Ω  
ALL INPUT PULSES  
90%  
10%  
R1 480Ω  
5V  
5V  
OUTPUT  
3.0V  
GND  
90%  
10%  
OUTPUT  
R2  
255Ω  
R2  
255Ω  
30 pF  
5 pF  
3 ns  
3 ns  
INCLUDING  
JIG AND  
SCOPE  
INCLUDING  
JIG AND  
SCOPE  
(b)  
(a)  
Equivalent to: THÉVENIN EQUIVALENT  
167Ω  
1.73V  
OUTPUT  
Switching Characteristics[4] Over the Operating Range  
-12  
-15  
Parameter  
Description  
Min.  
12  
3
Max.  
Min.  
15  
3
Max.  
Unit  
Read Cycle  
t
t
t
t
t
t
t
t
t
t
t
Read Cycle Time  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
RC  
Address to Data Valid  
12  
15  
AA  
Data Hold from Address Change  
OHA  
ACE  
DOE  
LZOE  
HZOE  
LZCE  
HZCE  
PU  
LOW to Data Valid  
LOW to Data Valid  
LOW to Low Z  
12  
6
15  
7
CE  
OE  
OE  
OE  
CE  
CE  
CE  
CE  
0
3
0
0
3
0
[5, 6]  
HIGH to High Z  
6
6
7
7
[6]  
LOW to Low Z  
[5, 6]  
HIGH to High Z  
LOW to Power-Up  
HIGH to Power-Down  
12  
15  
PD  
[7, 8]  
Write Cycle  
t
t
t
t
t
t
t
t
t
t
Write Cycle Time  
LOW to Write End  
12  
9
15  
10  
10  
0
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
ns  
WC  
CE  
SCE  
AW  
Address Set-Up to Write End  
Address Hold from Write End  
Address Set-Up to Write Start  
8
0
HA  
0
0
SA  
Pulse Width  
8
10  
8
WE  
PWE  
SD  
Data Set-Up to Write End  
6
Data Hold from Write End  
0
0
HD  
[6]  
HIGH to Low Z  
LOW to High Z  
3
3
WE  
WE  
LZWE  
HZWE  
[5, 6]  
6
7
Notes:  
4. Test conditions assume signal transition time of 3 ns or less, timing reference levels of 1.5V, input pulse levels of 0 to 3.0V, and output loading of the specified  
I
/I and 30-pF load capacitance.  
OL OH  
5. t  
, t  
, and t  
are specified with a load capacitance of 5 pF as in part (b) of AC Test Loads. Transition is measured ±500 mV from steady-state voltage.  
HZOE HZCE  
HZWE  
6. At any given temperature and voltage condition, t  
is less than t  
, t  
is less than t  
, and t  
is less than t  
for any given device.  
HZCE  
LZCE HZOE  
LZOE  
HZWE  
LZWE  
7. The internal write time of the memory is defined by the overlap of CE LOW and WE LOW. CE and WE must be LOW to initiate a write, and the transition of any  
of these signals can terminate the write. The input data set-up and hold timing should be referenced to the leading edge of the signal that terminates the write.  
8. The minimum write cycle time for Write Cycle no. 3 (WE controlled, OE LOW) is the sum of t  
and t  
.
SD  
HZWE  
Document #: 001-06425 Rev. **  
Page 3 of 8  
 
CY7C1019BN  
Data Retention Characteristics Over the Operating Range (L Version Only)  
Parameter Description Conditions  
for Data Retention No input may exceed V + 0.5V  
Min.  
Max.  
Unit  
V
V
I
V
2.0  
DR  
CC  
CC  
V
= V = 2.0V,  
CC  
DR  
Data Retention Current  
300  
µA  
ns  
CCDR  
> V – 0.3V,  
CE  
CC  
[3]  
t
t
Chip Deselect to Data Retention Time  
Operation Recovery Time  
0
V
> V – 0.3V or V < 0.3V  
CDR  
R
IN  
CC  
IN  
200  
µs  
Data Retention Waveform  
DATA RETENTION MODE  
> 2V  
3.0V  
3.0V  
V
V
CC  
DR  
t
t
R
CDR  
CE  
Switching Waveforms  
[9, 10]  
Read Cycle No. 1  
t
RC  
ADDRESS  
t
AA  
t
OHA  
DATA OUT  
PREVIOUS DATA VALID  
DATA VALID  
[10, 11]  
Read Cycle No. 2 (OE Controlled)  
ADDRESS  
CE  
t
RC  
t
ACE  
OE  
t
HZOE  
t
DOE  
t
HZCE  
t
LZOE  
HIGH  
IMPEDANCE  
HIGH IMPEDANCE  
DATA OUT  
DATA VALID  
t
LZCE  
t
PD  
ICC  
t
PU  
V
CC  
50%  
50%  
SUPPLY  
CURRENT  
ISB  
Notes:  
9. Device is continuously selected. OE, CE = V .  
IL  
10. WE is HIGH for read cycle.  
11. Address valid prior to or coincident with CE transition LOW.  
Document #: 001-06425 Rev. **  
Page 4 of 8  
 
CY7C1019BN  
Switching Waveforms (continued)  
[12, 13]  
Write Cycle No. 1 (CE Controlled)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
SA  
t
SCE  
t
t
HA  
AW  
t
PWE  
WE  
t
t
HD  
SD  
DATA I/O  
DATA VALID  
[12, 13]  
Write Cycle No. 2 (WE Controlled, OE HIGH During Write)  
t
WC  
ADDRESS  
t
SCE  
CE  
t
t
AW  
HA  
t
t
PWE  
SA  
WE  
OE  
t
t
SD  
HD  
DATA VALID  
DATA I/O  
IN  
NOTE 14  
t
HZOE  
Notes:  
12. Data I/O is high impedance if OE = V  
.
IH  
13. If CE goes HIGH simultaneously with WE going HIGH, the output remains in a high-impedance state.  
14. During this period the I/Os are in the output state and input signals should not be applied.  
Document #: 001-06425 Rev. **  
Page 5 of 8  
 
CY7C1019BN  
Switching Waveforms (continued)  
[13]  
Write Cycle No. 3 (WE Controlled, OE LOW)  
t
WC  
ADDRESS  
CE  
t
SCE  
t
t
HA  
AW  
t
SA  
t
PWE  
WE  
t
t
HD  
SD  
NOTE 14  
DATA I/O  
DATA VALID  
t
t
LZWE  
HZWE  
Truth Table  
CE  
H
L
OE  
WE  
X
I/O –I/O  
Mode  
Power  
0
7
X
L
High Z  
Power-Down  
Read  
Standby (I  
)
SB  
H
Data Out  
Data In  
High Z  
Active (I  
Active (I  
Active (I  
)
)
)
CC  
CC  
CC  
L
X
H
L
Write  
L
H
Selected, Outputs Disabled  
Ordering Information  
Speed  
(ns)  
Package  
Diagram  
Operating  
Range  
Ordering Code  
CY7C1019BN-12VC  
Package Type  
12  
51-85033 32-Lead 400-Mil Molded SOJ  
51-85095 32-Lead TSOP Type II  
Commercial  
CY7C1019BN-12ZC  
CY7C1019BN-12ZXC  
CY7C1019BN-15VC  
CY7C1019BN-15ZXC  
51-85095 32-Lead TSOP Type II (Pb-free)  
51-85033 32-Lead 400-Mil Molded SOJ  
51-85095 32-Lead TSOP Type II (Pb-free)  
15  
Commercial  
Please contact local sales representative regarding availability of these parts  
Document #: 001-06425 Rev. **  
Page 6 of 8  
 
CY7C1019BN  
Package Diagrams  
32-pin (400-mil) Molded SOJ (51-85033)  
51-85033-A  
51-85033-*B  
32-pin TSOP II (51-85095)  
51-85095-**  
All product or company names mentioned in this document may be the trademarks of their respective holders.  
Document #: 001-06425 Rev. **  
Page 7 of 8  
© Cypress Semiconductor Corporation, 2006. The information contained herein is subject to change without notice. Cypress Semiconductor Corporation assumes no responsibility for the use  
of any circuitry other than circuitry embodied in a Cypress product. Nor does it convey or imply any license under patent or other rights. Cypress products are not warranted nor intended to be  
used for medical, life support, life saving, critical control or safety applications, unless pursuant to an express written agreement with Cypress. Furthermore, Cypress does not authorize its  
products for use as critical components in life-support systems where a malfunction or failure may reasonably be expected to result in significant injury to the user. The inclusion of Cypress  
products in life-support systems application implDiesotwhantlothaedmfarnoumfacWturwerwa.sSsuommeasnaullarilssk.cofosmuc.hAulsleMaannduinadlsoinSgesaoricnhdeAmnndifieDsoCwypnrelosasda.gainst all charges.  
CY7C1019BN  
Document History Page  
Document Title: CY7C1019BN 128K x 8 Static RAM  
Document Number: 001-06425  
Orig. of  
Change  
REV.  
ECN NO.  
Issue Date  
Description of Change  
**  
423847  
See ECN  
NXR  
New Data Sheet  
Document #: 001-06425 Rev. **  
Page 8 of 8  
 

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